MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 84

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
CPOL – Clock polarity
This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock-data relation (see
Figure
6-10).
1 (set)
Steady high value at SCLK pin outside transmission window.
0 (clear) –
Steady low value at SCLK pin outside transmission window.
This bit should not be manipulated while the transmitter is enabled.
CPHA – Clock phase
This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works
in conjunction with the CPOL bit to produce the desired clock-data relation (see
Figure
6-10).
6
1 (set)
SCLK clock line activated at beginning of data bit.
0 (clear) –
SCLK clock line activated in middle of data bit.
This bit should not be manipulated while the transmitter is enabled.
Idle or preceding
transmission
clock
(CPOL = 0, CPHA = 0)
clock
(CPOL = 0, CPHA = 1)
clock
(CPOL = 1, CPHA = 0)
clock
(CPOL = 1, CPHA = 1)
data
Freescale
6-12
M = 0 (8 data bits)
Start
0
1
2
3
4
Start
LSB
*
LBCL bit controls last data clock
Figure 6-9 SCI data clock timing diagram (M=0)
SERIAL COMMUNICATIONS INTERFACE
Figure 6-9
Figure 6-9
Idle or next
Stop
transmission
*
*
*
*
5
6
7
MSB
Stop
MC68HC05B6
Rev. 4.1
and
and

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