- Components/
- Integrated Circuits (ICs)/
- Embedded - Microcontrollers/
MC68HC705B16CFN

MC68HC705B16CFN | |
---|---|
Manufacturer Part Number | MC68HC705B16CFN |
Description | IC MCU 2.1MHZ 15K OTP 52-PLCC |
Manufacturer | Freescale Semiconductor |
Series | HC05 |
MC68HC705B16CFN datasheet |
|
Specifications of MC68HC705B16CFN | |||
---|---|---|---|
Core Processor | HC05 | Core Size | 8-Bit |
Speed | 2.1MHz | Connectivity | SCI |
Peripherals | POR, WDT | Number Of I /o | 32 |
Program Memory Size | 15KB (15K x 8) | Program Memory Type | OTP |
Eeprom Size | 256 x 8 | Ram Size | 352 x 8 |
Voltage - Supply (vcc/vdd) | 4.5 V ~ 5.5 V | Data Converters | A/D 8x8b |
Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
Package / Case | 52-PLCC | Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant |
PrevNext
6.11
SCI registers
The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR,
and BAUD.
6.11.1
Serial communications data register (SCDR)
SCI data (SCDR)
The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts
as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it
is written.
Figure 6-1
shows this register as two separate registers, RDR and TDR. The RDR
6
provides the interface from the receive shift register to the internal data bus and the TDR provides
the parallel interface from the internal data bus to the transmit shift register.
The receive data register is a read-only register containing the last byte of data received from the
shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status
register is set to indicate that a byte has been transferred from the input serial shift register to the
SCDR. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as
shown in
Figure
6-1. All data is received with the least significant bit first.
The transmit data register (TDR) is a write-only register containing the next byte of data to be
applied to the transmit shift register from the internal data bus. As long as the transmitter is
enabled, data stored in the SCDR is transferred to the transmit shift register (after the current byte
in the shift register has been transmitted).
The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as
shown in
Figure
6-1. All data is received with the least significant bit first.
6.11.2
Serial communications control register 1 (SCCR1)
SCI control 1 (SCCR1)
The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character
format, the receiver wake-up feature and the options to output the transmitter clocks for
synchronous transmissions.
Freescale
6-10
Address
bit 7
bit 6
bit 5
bit 4
$0011
Address
bit 7
bit 6
bit 5
bit 4
$000E
R8
T8
M
SERIAL COMMUNICATIONS INTERFACE
State
bit 3
bit 2
bit 1
bit 0
on reset
0000 0000
State
bit 3
bit 2
bit 1
bit 0
on reset
WAKE CPOL CPHA LBCL Undefined
MC68HC05B6
Rev. 4.1
Related parts for MC68HC705B16CFN | |||
---|---|---|---|
Part Number | Description | Manufacturer | Datasheet |
![]() |
Freescale Semiconductor, Inc |
|
|
![]() |
HCMOS Microcontroller Unit | Freescale Semiconductor, Inc |
|
![]() |
Freescale Semiconductor, Inc |
|
|
![]() |
Freescale Semiconductor, Inc |
|
|
![]() |
Freescale Semiconductor, Inc |
|
|
![]() |
Freescale Semiconductor, Inc |
|
|
![]() |
Freescale Semiconductor, Inc |
|
|
![]() |
Freescale Semiconductor, Inc |
|
|
![]() |
Freescale Semiconductor, Inc |
|
|
![]() |
Freescale Semiconductor, Inc |
|
|
![]() |
Freescale Semiconductor, Inc | ||
![]() |
Freescale Semiconductor, Inc | ||
![]() |
Microcontrollers | FREESCALE [Freescale Semiconductor, Inc] |
|
![]() |
IC MCU 8BIT 44-QFP | Freescale Semiconductor |
|
![]() |
IC MCU 4MHZ 8K OTP 44-PLCC | Freescale Semiconductor |
|