MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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2.4.2
WAIT
2
The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode
consumes more power than STOP mode. All CPU action is suspended and the watchdog is
disabled, but the timer, A/D and SCI systems remain active and operate as normal (see flowchart
in
Figure
2-3). All other memory and registers remain unaltered and all parallel input/output lines
remain unchanged. The programming or erase mechanism of the EEPROM is also unaffected, as
well as the charge pump high voltage generator.
During WAIT mode the I-bit in the CCR is cleared to enable all interrupts. The INTE bit in the
miscellaneous register
(Section
sensed, the program counter vectors to the locations containing the start address of the interrupt
or reset service routine.
Any IRQ, timer (overflow, input capture or output compare) or SCI interrupt (in addition to a logic
low on the RESET pin) causes the processor to exit WAIT mode.
If a non-reset exit from WAIT mode is performed (i.e. timer overflow interrupt exit), the state of the
remaining systems will be unchanged.
If a reset exit from WAIT mode is performed the entire system reverts to the disabled reset state.
Note:
The stacking corresponding to an eventual interrupt to leave WAIT mode will only be
executed when leaving WAIT mode.
The following list summarizes the effect of WAIT mode on the modules of the MC68HC05B6.
– The watchdog timer functions according to the mask option selected; refer
to
Section 9.1.4.2
– The EEPROM is not affected; refer to
– The SCI is not affected; refer to
– The timer is not affected; refer to
– The PLM is not affected; refer to
– The A/D converter is not affected; refer to
– The I-bit in the CCR is cleared
2.4.2.1
Power consumption during WAIT mode
Power consumption during WAIT mode depends on how many systems are active. The power
consumption will be highest when all the systems (A/D, timer, EEPROM and SCI) are active, and
lowest when the EEPROM erase and programming mechanism, SCI and A/D are disabled. The
timer cannot be disabled in WAIT mode. It is important that before entering WAIT mode, the
programmer sets the relevant control bits for the individual modules to reflect the desired
functionality during WAIT mode.
Power consumption may be further reduced by the use of SLOW mode.
Freescale
MODES OF OPERATION AND PIN DESCRIPTIONS
2-8
2.5) is not affected by WAIT mode. When any interrupt or reset is
Section 3.7
Section 6.14
Section 5.7
Section 7.4
Section 8.4
MC68HC05B6
Rev. 4.1