MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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SFA — Slow or fast mode selection for PLMA (see
This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation
output.
1 (set)
Slow mode PLMA (4096 x timer clock period).
3
0 (clear) –
Fast mode PLMA (256 x timer clock period).
SFB — Slow or fast mode selection for PLMB (see
This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation
output.
1 (set)
Slow mode PLMB (4096 x timer clock period).
0 (clear) –
Fast mode PLMB (256 x timer clock period).
Note:
The highest speed of the PLM system corresponds to the frequency of the TOF bit
being set, multiplied by 256. The lowest speed of the PLM system corresponds to the
frequency of the TOF bit being set, multiplied by 16.
Warning: Because the SFA bit and SFB bit are not double buffered, it is mandatory to set the SFA
bit and SFB bit to the desired values before writing to the PLM registers; not doing so
could temporarily give incorrect values at the PLM outputs.
SM — Slow mode (see
1 (set)
The system runs at a bus speed 16 times lower than normal
(f
OSC
SCI, A/D and timer.
0 (clear) –
The system runs at normal bus speed (f
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
WDOG — Watchdog enable/disable (see
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
Once the watchdog is enabled, the WDOG bit acts as a reset mechanism for the watchdog
counter. Writing a’1’ to this bit clears the counter to its initial value and prevents a watchdog
timeout.
1 (set)
Watchdog counter cleared and enabled.
0 (clear) –
The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
Freescale
3-10
Section
Section
Section
2.4.3)
/32). SLOW mode affects all sections of the device, including
Section
9.1.4)
MEMORY AND REGISTERS
7.1)
7.1)
/2).
OSC
MC68HC05B6
Rev. 4.1