MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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9.1.1
Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (t
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high. The user must ensure that the voltage
on VDD has risen to a point where the MCU can operate properly by the time t
If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached
the specified minimum operating voltage. This may be accomplished by connecting an external
RC circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be
great enough to allow the oscillator circuit to stabilize.
During power-on reset, the RESET pin is driven low during a t
defined by a user specified mask option to be either 16 cycles or 4064 cycles (see
A software distinction between a power-on reset and an external reset can be made using the
POR bit in the miscellaneous register (see
9.1.2
Miscellaneous register
Miscellaneous
(1) The POR bit is set each time there is a power-on reset.
9
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
POR — Power-on reset bit
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set)
A power-on reset has occurred.
0 (clear) –
No power-on reset has occurred.
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in
Freescale
9-2
PORL
Section
9.1.2).
Address
bit 7
bit 6
bit 5
bit 4
(1)
$000C POR
INTP
INTN
INTE
Section
3.8.
RESETS AND INTERRUPTS
) from when the
PORL
has elapsed.
PORL
delay start-up sequence. t
is
PORL
Section
1.2).
State
bit 3
bit 2
bit 1
bit 0
on reset
(2)
SFA
SFB
SM WDOG
?001 000?
MC68HC05B6
Rev. 4.1