MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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OR — Overrun error flag
This bit is set when a new byte is ready to be transferred from the receiver shift register to the
receiver data register and the receive data register is already full (RDRF bit is set). Data transfer
is inhibited until the RDRF bit is cleared. Data in the serial communications data register is valid
in this case, but additional data received during an overrun condition (including the byte causing
the overrun) will be lost.
The OR bit is cleared when the serial communications status register is accessed (with OR set)
followed by a read of the serial communications data register.
NF — Noise error flag
This bit is set if there is noise on a ‘valid’ start bit, any of the data bits or on the stop bit. The NF
bit is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not set
until the RDRF flag is set. Each data bit is sampled three times as described in
Section
6.7.
The NF bit represents the status of the byte in the serial communications data register. For the
6
byte being received (shifted in) there will be also a ‘working’ noise flag, the value of which will be
transferred to the NF bit when the serial data is loaded into the serial communications data
register. The NF bit does not generate an interrupt because the RDRF bit gets set with NF and
can be used to generate the interrupt.
The NF bit is cleared when the serial communications status register is accessed (with NF set)
followed by a read of the serial communications data register.
FE — Framing error flag
This bit is set when the word boundaries in the bit stream are not synchronized with the receiver
bit counter (generated by the reception of a logic zero bit where a stop bit was expected). The FE
bit reflects the status of the byte in the receive data register and the transfer from the receive shifter
to the receive data register is inhibited by an overrun. The FE bit is set during the same cycle as
the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag inhibits
further transfer of data into the receive data register until it is cleared.
The FE bit is cleared when the serial communications status register is accessed (with FE set)
followed by a read of the serial communications data register.
MC68HC05B6
SERIAL COMMUNICATIONS INTERFACE
Freescale
Rev. 4.1
6-17