MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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E1LAT — EEPROM programming latch enable bit
1 (set)
Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
0 (clear) –
Data can be read from the EEPROM. The E1ERA bit and the E1PGM
bit are reset to zero when E1LAT is ‘0’.
STOP, power-on and external reset clear the E1LAT bit.
Note:
After the t
ERA1
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM — EEPROM charge pump enable/disable
1 (set)
Internal charge pump generator switched on.
0 (clear) –
Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in
E1ERA E1LAT E1PGM
0
0
0
1
1
Note:
The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.
14
Freescale
H-10
erase time or t
programming time, the E1LAT bit has to be reset
PROG1
Table H-3 EEPROM control bits description
Description
0
0
Read condition
1
0
Ready to load address/data for program/erase
1
1
Byte programming in progress
1
0
Ready for byte erase (load address)
1
1
Byte erase in progress
MC68HC705B32
Table
H-3.
MC68HC05B6
Rev. 4.1