IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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ACEX 1K Programmable Logic Device Family Data Sheet
Figure 8. ACEX 1K Logic Element
data1
Look-Up
data2
data3
data4
labctrl1
labctrl2
Chip-Wide
Reset
labctrl3
labctrl4
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the LUT’s
output drives the LE’s output.
The LE has two outputs that drive the interconnect: one drives the local
interconnect, and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The ACEX 1K architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports high-
speed counters and adders, and the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in a LAB and all LABs in the same row. Intensive use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of these chains
should be limited to speed-critical portions of a design.
16
Carry-In
Cascade-In
Carry
Cascade
Table
Chain
Chain
(LUT)
Clear/
Preset
Logic
Clock
Select
Carry-Out
Cascade-Out
Register Bypass
Programmable
Register
PRN
D
Q
ENA
CLRN
Altera Corporation
To FastTrack
Interconnect
To LAB Local
Interconnect