IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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Table 27. External Reference Timing Parameters
Symbol
t
Register-to-register delay via four LEs, three row interconnects, and four local
DRR
interconnects
Table 28. External Timing Parameters
Symbol
t
Setup time with global clock at IOE register
INSU
t
Hold time with global clock at IOE register
INH
t
Clock-to-output delay with global clock at IOE register
OUTCO
t
Setup time with global clock for registers used in PCI designs
PCISU
t
Hold time with global clock for registers used in PCI designs
PCIH
t
Clock-to-output delay with global clock for registers used in PCI designs
PCICO
Table 29. External Bidirectional Timing Parameters
Symbol
t
Setup time for bidirectional pins with global clock at same-row or same-
INSUBIDIR
column LE register
t
Hold time for bidirectional pins with global clock at same-row or same-column
INHBIDIR
LE register
t
Clock-to-output delay for bidirectional pins with global clock at IOE register
OUTCOBIDIR
t
Synchronous IOE output buffer disable delay
XZBIDIR
t
Synchronous IOE output buffer enable delay, slow slew rate = off
ZXBIDIR
Notes to tables:
(1)
External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
(2)
Contact Altera Applications for test circuit specifications and test conditions.
(3)
These timing parameters are sample-tested only.
(4)
This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, Revision 2.2.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Tables 27
through
29
describe the ACEX 1K external timing parameters
and their symbols.
Note (1)
Parameter
Parameter
Note (3)
Parameter
Conditions
(2)
Conditions
(3)
(3)
(3)
(3),
(4)
(3),
(4)
13
(3),
(4)
Conditions
CI = 35 pF
CI = 35 pF
CI = 35 pF
59