IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
2
-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2 for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
Operate with a 2.5-V internal supply voltage
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
ClockLock
TM
and ClockBoost
clock skew, and clock multiplication
Built-in, low-skew clock distribution trees
100% functional testing of all devices; test vectors or scan chains
are not required
Pull-up on I/O pins before and during configuration
Flexible interconnect
FastTrack
®
Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
Powerful I/O pins
Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
Clamp to V
user-selectable on a pin-by-pin basis
CCIO
Supports hot-socketing
TM
options for reduced clock delay,
Altera Corporation