IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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Figure 14. ACEX 1K Interconnect Resources
I/O Element (IOE)
IOE
IOE
Row
LAB
Interconnect
A1
Column
Interconnect
IOE
IOE
LAB
B1
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
IOE
IOE
IOE
IOE
LAB
A2
LAB
B2
IOE
IOE
IOE
IOE
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time
or as an output register for data that requires fast clock-to-output
performance. In some cases, using an LE register for an input register will
result in a faster setup time than using an IOE register. IOEs can be used
as input, output, or bidirectional pins. The compiler uses the
programmable inversion option to invert signals from the row and
column interconnect automatically where appropriate. For bidirectional
registered I/O implementation, the output register should be in the IOE
and the data input and output enable registers should be LE registers
placed adjacent to the bidirectional pin.
I/O registers.
See Figure 17
for details.
IOE
IOE
LAB
A3
To LAB A5
To LAB A4
Cascade &
LAB
B3
Carry Chains
To LAB B5
To LAB B4
IOE
IOE
Figure 15
shows the bidirectional
IOE
IOE
See Figure 16
for details.
IOE
13
IOE
29