IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part NumberEP1K10TC100-3
DescriptionIC ACEX 1K FPGA 10K 100-TQFP
ManufacturerAltera
SeriesACEX-1K®
EP1K10TC100-3 datasheet
 


Specifications of EP1K10TC100-3

Number Of Logic Elements/cells576Number Of Labs/clbs72
Total Ram Bits12288Number Of I /o66
Number Of Gates56000Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface MountOperating Temperature0°C ~ 70°C
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-1027  
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ACEX 1K Programmable Logic Device Family Data Sheet
In addition to the six clear and preset modes, ACEX 1K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset.
of how to setup the preset and clear inputs for the desired functionality.
Figure 12. ACEX 1K LE Clear & Preset Modes
Asynchronous Clear
VCC
PRN
D
Q
CLRN
labctrl1 or
labctrl2
Chip-Wide Reset
Asynchronous Load with Clear
NOT
labctrl1
(Asynchronous
Load)
data3
(Data)
NOT
labctrl2
(Clear)
Chip-Wide Reset
Asynchronous Load with Preset
NOT
labctrl1
(Asynchronous
Load)
labctrl2
(Preset)
data3
(Data)
NOT
24
Asynchronous Preset
Chip-Wide Reset
labctrl1 or
labctrl2
PRN
D
Q
CLRN
VCC
Asynchronous Load without Clear or Preset
(Asynchronous
PRN
D
Q
CLRN
PRN
D
CLRN
Chip-Wide Reset
Figure 12
shows examples
Asynchronous Preset & Clear
labctrl1
PRN
D
CLRN
labctrl2
Chip-Wide Reset
NOT
labctrl1
Load)
data3
(Data)
NOT
Chip-Wide Reset
Q
Altera Corporation
Q
PRN
D
Q
CLRN