MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 108

• Manufacturer Part Number: MC68HC711KS2MFN4
• Description: 32K EPROM - SLOW MODE
• Manufacturer: Freescale Semiconductor

Resets and Interrupts
5.3.3.1 System Configuration Register
Technical Data
108
NOTE:
NOTE:
Address: $003F
Three registers are involved in COP operation:
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
In normal modes, COP is enabled out of reset and does not depend on
software action. To disable the COP system, set the NOCOP bit in the
CONFIG register (see
operating modes, the COP system is initially inhibited by the disable
resets (DISR) control bit in the TEST1 register. The DISR bit can
subsequently be written to 0 to enable COP resets.
CONFIG is writable once in normal modes and writable at any time in
special modes.
NOCOP — COP System Disable Bit
Reset:
Read:
Write:
•
•
•
0 = COP enabled
1 = COP disabled
The CONFIG register contains a bit which determines whether the
COP system is enabled or disabled.
The OPTION register contains two bits which determine the COP
timeout period.
The COPRST register must be written by software to reset the
watchdog timer.
Figure 5-1. System Configuration Register (CONFIG)
ROMAD
Bit 7
—
Resets and Interrupts
6
1
1
Figure
CLKX
—
5
5-1). In special test and bootstrap
PAREN
—
4
NOSEC
3
1
NOCOP
—
2
M68HC11K Family
ROMON
—
1
MOTOROLA
EEON
Bit 0
—