MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 141
MC68HC711KS2MFN4
Manufacturer Part Number
MC68HC711KS2MFN4
Description
32K EPROM - SLOW MODE
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711KS2MFN4.pdf
(290 pages)
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M68HC11K Family
MOTOROLA
NOTE:
Figure 6-7. System Configuration Options 2 Register (OPT2)
Address: $0007
Address: $0038
DDC[7:0] — Data Direction for Port C Bits
CWOM — Port C Wired-OR Mode Bit
IRVNE — Internal Read Visibility/Not E Bit
IRVNE can be written only once after reset. The default value of IRVNE
after reset is low.
Reset:
Reset:
Read:
Read:
Write:
Write:
In expanded modes, setting this bit drives MCU’s internal data bus on
port C.
In single-chip modes, setting this bit inhibits the E clock driver, and the
E pin is pulled low
Figure 6-6. Port C Data Direction Register (DDRC)
0 = Input
1 = Output
0 = Port C operates normally.
1 = Port C outputs are open drain.
0 = No internal read visibility on external data bus
1 = Data from internal reads is driven on port C.
0 = E clock drives the E pin.
1 = E pin is driven low.
1. Not available on KS devices
LIRDV
DDC7
Bit 7
Bit 7
0
0
Parallel Input/Output
CWOM
DDC6
6
0
6
0
STRCH
DDC5
5
0
5
0
(1)
IRVNE
DDC4
—
4
0
4
DDC3
LSBF
3
0
3
0
DDC2
SPR2
2
0
2
0
Parallel Input/Output
DDC1
XDV1
1
0
1
0
Technical Data
DDC0
XDV0
Bit 0
Bit 0
Port C
0
0
141
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