MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 186

• Manufacturer Part Number: MC68HC711KS2MFN4
• Description: 32K EPROM - SLOW MODE
• Manufacturer: Freescale Semiconductor

Timing System
Technical Data
186
NOTE:
Figure 9-2
A pin control block includes logic for timer functions and for
general-purpose I/O. This block contains the edge-detection logic for
pins PA[2:0] as well as the control logic that enables edge selection for
the input capture trigger.
Reading the port A register returns the actual pin level on any pin
functioning as an input, and the logic level of the internal pin driver (NOT
the pin level) on any pin functioning as an output. This is true whether
the pins are configured for timer functions or GPIO. Writing to port A pins
configured for timer functions has no visible effect; the writes are latched
but do not drive the pins.
Registers common to both the input capture and output compare
functions include:
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
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PA[2:0] can serve either as input capture pins IC[1:3] or as
general-purpose input/output (GPIO).
PA[6:4] can serve either as drivers for output compare functions
OC[2:4] or GPIO.
PA3 can be used for GPIO, input capture 4, output compare 5, or
output compare 1.
Output compare 1 (OC1) has extra control logic which gives it
optional control of any combination of the PA[7:3] pins.
The PA7 pin can be used as a GPIO pin, as an input to the pulse
accumulator, or as an OC1 output pin.
Timer counter register (TCNT)
Timer interrupt flag 2 (TFLG2)
Timer interrupt mask 2 (TMSK2)
Data direction register A (DDRA)
Pulse accumulator control register (PACTL)
shows the capture/compare system block diagram. The port
Timing System
M68HC11K Family
MOTOROLA