MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 136

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MC68HC711KS2MFN4

Manufacturer Part Number
MC68HC711KS2MFN4
Description
32K EPROM - SLOW MODE
Manufacturer
Freescale Semiconductor
Datasheet

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Parallel Input/Output
6.2 Introduction
Technical Data
136
The M68HC11K series MCUs contain eight input/output (I/O) ports, A
through H. All ports can provide general-purpose I/O (GPIO) as well as
their specialized functions, as explained in
summarized in
Each of the ports has an associated data register (PORTx). Each port,
except port E, also has an associated data direction register (DDRx).
When a port is configured for GPIO, its DDR determines whether port
pins function as inputs or outputs. A port’s special functions override the
DDR when they are enabled.
Writes to any port, except port E, are stored in internal latches. The
latches drive the port pins only when they are configured as
general-purpose outputs.
When software reads a port pin configured for GPIO, the MCU returns
the physical pin level, not the port register value. This applies to both
inputs and outputs. The only exception applies to ports C and D in
wired-OR mode. When they are configured as outputs, a read returns
the pin driver levels.
1. KS devices do not contain port G[6:0], so they have only one bidirectional pin on this port.
2. KS devices do not contain port H[7:4], so they have only four bidirectional pins on this port.
Port G
Port A
Port B
Port C
Port D
Port E
Port H
Port F
Port
Input
Pins
8
Parallel Input/Output
Table
Output
Pins
Table 6-1. Port Configuration
6-1.
Bidirectional
Pins
8
8
8
8
8
6
8
(1)
(2)
2.11 Port Signals
Timer
High-order address
Data bus
SCI and SPI
A/D converter
Low-order address
Memory expansion
Chip selects and PWM
Shared Functions
M68HC11K Family
MOTOROLA
and

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