MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 249

• Manufacturer Part Number: MC68HC711KS2MFN4
• Description: 32K EPROM - SLOW MODE
• Manufacturer: Freescale Semiconductor

11.5 Memory Expansion Examples
M68HC11K Family
MOTOROLA
Address: $005A
IOS[A:B] — CSIO Stretch Select Bits
GP1S[A:B] — CSGP1 Stretch Select Bits
GP2S[A:B] — CSGP2 Stretch Select Bits
PCS[A:B] — CSPROG Stretch Select Bits
The first example, shown in
64 Kbytes of external memory to be accessed through a single 8-Kbyte
window. To access eight Kbytes, or 2
need 13 address lines, ADDR[12:0]. The number of memory banks
needed is the total memory, 64 Kbytes divided by the window size, eight
Kbytes. This yields eight memory banks, or 2
lines are required, so expansion address lines XA[15:13] replace CPU
address lines ADDR[15:13].
schematic drawing of this system.
Reset:
Read:
Write:
Each of these pairs of bits contain the binary number of cycles of clock
stretch, as shown in
Figure 11-14. Chip Select Clock Stretch Register (CSCSTR)
IOSA
Memory Expansion and Chip Selects
Bit 7
0
Table 11-9. CSCSTR Bits Versus Clock Cycles
IOSB
6
0
Bit [A:B]
0 0
0 1
1 0
1 1
Table
GP1SA
5
0
Figure 11-15
Figure 1-1
11-9.
GP1SB
4
0
13
address locations, the CPU will
shows a memory map and
GP2SA
Memory Expansion and Chip Selects
contains a system with
3
0
Clock Stretch
3
2 cycles
3 cycles
. Thus, three expansion
1 cycle
Memory Expansion Examples
None
GP2SB
2
0
PCSA
1
0
Technical Data
PCSB
Bit 0
0
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