MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 176

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MC68HC711KS2MFN4

Manufacturer Part Number
MC68HC711KS2MFN4
Description
32K EPROM - SLOW MODE
Manufacturer
Freescale Semiconductor
Datasheet

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Serial Peripheral Interface (SPI)
8.6.2 Serial Peripheral Status Register
Technical Data
176
Address: $0029
SPIF — SPI Transfer Complete Flag
WCOL — Write Collision Bit
MODF — Mode Fault Bit
Reset:
Read:
Write:
SPIF is set upon completion of data transfer between the processor
and the external device. If SPIF goes high, and if SPIE is set, a serial
peripheral interrupt is generated. To clear the SPIF bit, read the SPSR
with SPIF set, then access the SPDR. Unless SPSR is read (with
SPIF set) first, attempts to write SPDR are inhibited.
Clearing the WCOL bit is accomplished by reading the SPSR (with
WCOL set) followed by an access of SPDR.
To clear the MODF bit, read the SPSR (with MODF set), then write to
the SPCR.
0 = No write collision
1 = Write collision
0 = No mode fault
1 = Mode fault
Figure 8-4. Serial Peripheral Status Register (SPSR)
SPIF
Bit 7
0
Serial Peripheral Interface (SPI)
WCOL
6
0
5
0
0
MODF
4
0
3
0
0
2
0
0
M68HC11K Family
1
0
0
MOTOROLA
Bit 0
0
0

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