MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 80
MC68HC711KS2MFN4
Manufacturer Part Number
MC68HC711KS2MFN4
Description
32K EPROM - SLOW MODE
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711KS2MFN4.pdf
(290 pages)
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Operating Modes and On-Chip Memory
Technical Data
80
Address: $003C
1. The values of the RBOOT, SMOD, and MDA bits at reset depend on the mode during
Table 4-3
latched. The HPRIO register is illustrated in
RBOOT — Read Bootstrap ROM Bit
SMOD — Special Mode Select Bit
Reset:
Read:
Write:
MODB
initialization.
In special modes, this bit enables the bootloader ROM
In normal modes this bit is clear and cannot be written.
This bit reflects the inverse of the MODB input pin at the rising edge
of RESET. If MODB is low during reset, SMOD is set; if MODB is high
during reset, SMOD is cleared. Software can clear the SMOD bit, but
cannot set it. Thus, it is possible for software to change the operating
1
1
0
0
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and located in map at $BE00–$BFFF
Inputs
RBOOT
Operating Modes and On-Chip Memory
Bit 7
—
summarizes the inputs, modes selected, and register bits
MODA
(1)
Table 4-3. Hardware Mode Select Summary
Figure 4-2. Highest Priority I-Bit Interrupt
0
1
0
1
and Miscellaneous Register (HPRIO)
SMOD
—
6
(1)
Special bootstrap
MDA
—
5
Special test
Single-chip
Expanded
(1)
Mode
PSEL4
4
0
PSEL3
3
0
Figure
RBOOT
Control Bits in HPRIO
0
0
1
0
PSEL2
Latched at Reset
2
1
4-2.
SMOD
M68HC11K Family
PSEL1
0
0
1
1
1
1
MOTOROLA
MDA
PSEL0
Bit 0
0
1
0
1
0
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