MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 114
MC68HC711KS2MFN4
Manufacturer Part Number
MC68HC711KS2MFN4
Description
32K EPROM - SLOW MODE
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711KS2MFN4.pdf
(290 pages)
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Resets and Interrupts
Technical Data
114
LSBF — Least Significant Bit (LSB) First Enable Bit
SPR2 — SPI Clock Rate Selected Bit
XDV[1:0] — XOUT Clock Divide Select Bits
XDV
[1:0]
0 0
0 1
1 0
1 1
For detailed information, refer to
Interface
This bit adds a divide-by-four to the SPI clock chain. For detailed
information, refer to
These bits control the frequency of the clock driven out of the
XOUT pin, if enabled by the CLKX bit on the CONFIG register. See
Table 5-4
1 = Data is transferred LSB first.
0 = Data is transferred MSB (most significant bit) first.
XOUT = EXTAL
Divided By
(SPI).
Resets and Interrupts
1
4
6
8
Table 5-4. XOUT Clock Divide Select
Section 8. Serial Peripheral Interface
Frequency at
EXTAL =
1.3 MHz
8 MHz
8 MHz
2 MHz
1 MHz
Section 8. Serial Peripheral
Frequency at
EXTAL =
1.5 MHz
12 MHz
12 MHz
3 MHz
2 MHz
M68HC11K Family
Frequency at
EXTAL =
2.7 MHz
16 MHz
16 MHz
MOTOROLA
4 MHz
2 MHz
(SPI).
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