PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet
PEF 22508 E V1.1-G
Specifications of PEF 22508 E V1.1-G
PEF22508EV11GXP
SP000029953
Related parts for PEF 22508 E V1.1-G
PEF 22508 E V1.1-G Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.9.6.2 Programming with TXP(16:1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 54 FSC Timing ...
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List of Tables Table 1 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 52 JTAG Boundary Scan Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preface TM The OctalLIU channel E1/T1/J1 Line interface Component designed to fulfill all required interfacing between 8 analog E1/T1/J1 lines and 8 digital framers. The digital functions as well as the analog characteristics can be ...
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Introduction TM The OctalLIU is the latest addition to Infineon’s family of sophisticated E1/T1/J1 Line interface Components. This monolithic 8 channel device is designed to fulfill all required interfacing between eight analog E1/T1/J1 lines and eight digital framer interfaces ...
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Octal E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications TM OctalLIU Version 1.1 1.1 Features Line Interface • High-density, generic interface for all E1/T1/J1 applications • Eight Analog receive and transmit circuits for long-haul and short-haul applications • E1 ...
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Alarm and performance monitoring per second 16-bit counter for code violations, PRBS bit errors • Insertion and extraction of alarm indication signals (AIS) • Single-bit defect insertion • Flexible clock frequency for receiver and transmitter • Dual elastic stores ...
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... TMS Scan TCK TRS Interface TDO XL1(8:1) Transmit XL2(8:1) Line XL3(8:1) Interface XL4(8:1) Figure 1 Logic Symbol Data Sheet OctalLIU TM PEF 22508 E V1.1 P-LBGA256 (SCI- or Microprocessor Interface SPI-Bus) 14 OctalLIU PEF 22508 E Introduction RDO(8:1) Receive RPA(8:1) Digital RPB(8:1) Interface RPC(8:1) FCLKR(8:1) XDI(8:1) Transmit ...
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Typical Applications Figure 2 shows a multiple link application E1/T1/J1 Receive & Transmit Figure 2 Typical Multiple Link Application Bidirectional Line #1 Bidirectional Line #2 Figure 3 Typical Multiple Repeater Application between line #1 and Line #2 ...
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Pin Descriptions In this chapter the function and placement of all pins are described. 2.1 Pin Diagram PG-LBGA-256 (top view) Figure 4 shows the ball layout of the OctalLIU Reserved XPB8 XPA8 FCLKX8 FCLKR8 ...
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Pin Definitions and Functions The following table describes all pins and their functions: Table 1 I/O Signals Pin No. Ball Name No. Operation Mode Selection and Device Initialization B3 RES B6 IM1 B4 IM0 Asynchronous and Serial Micro Controller ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. 1F D15 PLL10 2F D14 PLL9 F3 D13 PLL8 F4 D12 PLL7 G1 D11 PLL6 G2 D10 PLL5 G3 D9 PLL4 H1 D8 PLL3 H2 D7 PLL2 J1 D6 PLL1 ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No SCI_CLK SCLK K1 D1 SCI_RXD SDI K2 D0 SCI_TXD SDO G15 ALE H16 RD DS Data Sheet Pin Type Buffer Function Type IO PU Data Bus ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. H15 DBW H13 BHE BLE H12 CS H11 INT G14 READY DTACK Line Interface Receiver Data Sheet Pin Type Buffer Function Type I PU Write Enable Intel ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. A6 RL1.1 ROID1 A8 RL2.1 A7 RLS21 A4 RL1.2 ROID2 A2 RL2.2 A3 RLS22 T4 RL1.3 ROID3 T2 RL2.3 T3 RLS23 Data Sheet Pin Type Buffer Function Type I (analog) ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. T6 RL1.4 ROID4 T7 RL2.4 R7 RLS24 T11 RL1.5 ROID5 T9 RL2.5 T10 RLS25 T13 RL1.6 ROID6 T15 RL2.6 T14 RLS26 Data Sheet Pin Type Buffer Function Type I (analog) ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. A13 RL1.7 ROID7 A15 RL2.7 A14 RLS27 A11 RL1.8 ROID8 A10 RL2.8 B10 RLS28 Line Interface Transmitter D7 XL1.1 XOID1 D6 XL2.1 Data Sheet Pin Type Buffer Function Type I ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. C7 XL3.1 C6 XL4.1 D4 XL1.2 XOID2 D3 XL2.2 C4 XL3.2 C3 XL4.2 N4 XL1.3 XOID3 Data Sheet Pin Type Buffer Function Type I (analog) – Transmit Line 3, port ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. N3 XL2.3 XFM3 P4 XL3.3 P3 XL4.3 M7 XL1.4 XOID4 M6 XL2.4 N7 XL3.4 N6 XL4.4 Data Sheet Pin Type Buffer Function Type O – Transmit Line 2, port 3 ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. N11 XL1.5 XOID5 N10 XL2.5 P11 XL3.5 P10 XL4.5 N14 XL1.6 XOID6 N13 XL2.6 P14 XL3.6 P13 XL4.6 Data Sheet Pin Type Buffer Function Type O – Transmit Line 1, ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. D14 XL1.7 XOID7 D13 XL2.7 C14 XL3.7 C13 XL4.7 E11 XL1.8 XOID8 E10 XL2.8 D11 XL3.8 D10 XL4.8 Clock Signals Data Sheet Pin Type Buffer Function Type O – Transmit ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. J6 MCLK G13 SYNC G12 FSC Digital (Framer) Interface Receive C2 RDO1 C1 FCLKR1 E4 RDO2 E1 FCLKR2 L6 RDO3 K4 FCLKR3 M3 RDO4 M1 FCLKR4 P15 RDO5 P16 FCLKR5 ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. F13 FCLKR7 E13 RDO8 E16 FCLKR8 Digital (Framer) Interface Transmit E5 XDI1 D1 FCLKX1 F7 XDI2 F8 FCLKX2 L5 XDI3 L3 FCLKX3 P2 XDI4 N1 FCLKX4 M11 XDI5 M12 FCLKX5 ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. B1 RPA1 D2 RPB1 E7 RPC1 B1 RPA1 D2 RPB1 E7 RPC1 B1 RPA1 D2 RPB1 E7 RPC1 B1 RPA1 D2 RPB1 E7 RPC1 B1 RPA1 D2 RPB1 E7 RPC1 ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. E6 RPA2 E8 RPB2 E9 RPC2 L4 RPA3 L2 RPB3 L1 RPC3 M4 RPA4 M5 RPB4 N2 RPC4 Data Sheet Pin Type Buffer Function Type I/O PU/– Receive Multifunction Pins ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. R16 RPA5 N15 RPB5 N16 RPC5 M13 RPA6 L13 RPB6 L15 RPC6 F16 RPA7 F14 RPB7 F10 RPC7 Data Sheet Pin Type Buffer Function Type I/O PU/– Receive Multifunction Pins ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. E12 RPA8 D15 RPB8 F11 RPC8 E3 XPA1 E2 XPB1 E3 XPA1 E2 XPB1 E3 XPA1 E2 XPB1 E3 XPA1 E2 XPB1 Data Sheet Pin Type Buffer Function Type I/O ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. E3 XPA1 E2 XPB1 E3 XPA1 E2 XPB1 E3 XPA1 E2 XPB1 E3 XPA1 E2 XPB1 E3 XPA1 E2 XPB1 F5 XPA2 F6 XPB2 L7 XPA3 M2 XPB3 Data Sheet ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. P1 XPA4 R1 XPB4 M14 XPA5 M15 XPB5 L12 XPA6 L11 XPB6 Data Sheet Pin Type Buffer Function Type I/O PU/– Transmit Multifunction Pins A and B, port 4 Depending ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. E14 XPA7 E15 XPB7 4 C16 XPA8 4 B16 XPB8 Power Supply V 7B DDR1 V 5B DDR2 V 4R DDR3 6R V DDR4 V 11R DDR5 V 12R DDR6 ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No DDX2 DDX3 DDX4 DDX5 9P V 12N DDX6 12P V 12C DDX7 12D V 9C DDX8 ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No 12A 12B 14B 15B 10C 11C 10G 10H 10J ...
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Table 1 I/O Signals (cont’d) Pin No. Ball Name No. P6 TRS M9 TDI M8 TMS R9 TCK R10 TDO Note open drain output PU = input or input/output comprising an internal pull-up device To override the internal ...
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Pin Strapping Some pins are used for selection of functional modes of the OctalLIU Table 2 Overview about the Pin Strapping PIN Pin Strapping is used IM(1:0) Always A(5:0) Only in SCI interface mode Defines the six Lisps of ...
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Functional Description 3.1 Hardware TM The OctalLIU always requires two supply voltages, 1.8 V and 3.3 V. 3.2 Software TM The OctalLIU device contains analog and digital function blocks that are configured and controlled by an external microprocessor or ...
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Block Diagram Figure 5 shows the block diagram of the OctalLIU RLS(1:8) Long+Short RL1/ROID(1:8) Haul Receive RL2(1:8) Line Interface Clock & Data Recovery Long+Short XL1/XOID(1:8) Haul Transmit XL2(1:8) Line Interface XL3(1:8) XL4(1:8) Boundary Scan JTAG IM(1:0) TDI,TMS,TCK,TRS,TDO Figure 5 ...
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The communication between the external micro controller and the OctalLIU accessible registers. The interface can be configured as Intel or Motorola type with a selectable data bus width bits. The external micro controller transfers data to ...
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Intel (Address Motorola (Address n) Data lines D15 n: even address 3.5.2 Serial Micro Controller Interfaces Two serial interfaces are included to enable device programming and controlling:- Slave Serial Control Interface (SCI) - Slave Serial Peripheral Interface ...
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Figure 6 SCI Interface Application with Point To Point Connections Micro-processor or Interworking Device Figure 7 SCI Interface Application with Multipoint To Multipoint Connection The following configurations of the SCI interface of the OctalLIU command into the SCI configuration register ...
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Figure 8 SCI Message Structure of OctalLIU Every write into or read from a register of the OctalLIU (micro con roller) and is then confirmed by an acknowledge message ACK from the OctalLIU configuration automatic acknowledgement is set (bit ACK_EN, ...
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SCI HDLC Basic Frame Structure Flag Address Write CMD Frame Structure Source Destination 01111110 Address Read CMD Frame Structure Source Destination 01111110 Address Write ACK Frame Structure Source Destination 01111110 Address Read ACK Frame Structure Source Destination 01111110 Address Figure ...
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VFR RDO Figure 11 Read Status Byte (RSTA) byte of the SCI Acknowledge (ACK) Table 6 Read Status Byte (RSTA) Byte of the SCI Acknowledge (ACK) Field Bit Description VFR 7 Valid Frame. Indicates whether a valid frame ...
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Figure 12 and Figure 13 show the read and the write operation respectively. The start of a read or write operation is marked by the falling edge of the chip select signal CS whereas the end of the operations is ...
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VISPLL GIS2 PLLLC PLLL GIMR PLL PLLLS not visible Channel Interrupt Status Register CIS , global GIS8 GIS7 GIS6 GIS5 INT GIS4 GIS3 GIS2 GIS1 Figure 14 Interrupt Status Registers Each interrupt indication bit of the registers ISR can be ...
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Masked Interrupts Visible in Status Registers • The “Global” Interrupt Status register (GIS) indicates those interrupt status registers with active interrupt indications (bits GIS.ISR(7:0)). • An additional interrupt mode can be selected per port via bit GCR.VIS (GCR). In this ...
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TAP controller reset TRS clock TCK test control TMS data in TDI enable TDO data out Figure 15 Block Diagram of Test Access Port and Boundary Scan After switching on the device (power-on), a reset signal has to be applied ...
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SAMPLE Is a test mode which provides a snapshot of pin levels during normal operation. IDCODE A 32-bit identification register is serially read out on pin TDO. It contains the version number (4 bits), the device code (16 bits) and ...
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MCLK PLL D(15:5) Figure 16 Flexible Master Clock Unit 3.5.5.1 PLL (Reset and Configuring) If the (asynchronous) micro controller interface mode is selected by IM(1:0) the PLL must be configured • By programming of the registers GCM5 and GCM6 in ...
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Table 11 Conditions for a PLL Reset Reset Pin GCM2.VFREQ_EN Used controller Active X (will be set to ´1´ by reset) Inactive -> -> 0 3.6 Line Coding and Framer Interface Modes An overview ...
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Table 12 Line Coding and Framer Interface Modes (cont’d) Line Code, Register Bits Framer IF Mode FMR0.RC, LIM3.DRR 0 -> -> 0 3.7 Receive Path An overview about the receive path of one channel of the OctalLIU ...
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A Recovered clock Recovered clock to selection DCO_R C RCLK SYNC Figure 18 Recovered and Receive Clock Selection 3.7.1 Receive Line Interface For data input, two different data types are supported (see also • Ternary coded signals received ...
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Multi Function Ports must be configured as Receive Line Termination (RLT) input. For controlling of the analog switch a logical equivalence is build out of RLT and the register bit LIM0.RTRS if RLT ...
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Table 14 External Component Recommendations (Monitoring) 1) Parameter Characteristic Impedance (Ohm 330 ...
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An overview about the tristate configurations of RDOP and RCLK is given in Table 15 Tristate Configurations for the RDO and RCLK pins DIC3.RRTRI / DIC3.RRTRI exor RTDMT if RTDMT is selected on multi function port ...
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E1/T1/J1 Transmit Line E1/T1/J1 Receive Line Figure 22 Long Haul Redundancy Application using the Analog Switch (shown for one line) Table 17 Redundancy Application using the Analog Switch, switching with only one board signal Configuration XLT, XLT PC1.XPC1(3:0) RTDMT PC1.RPC1(3:0) ...
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Recovery: In general the recovery procedure starts after detecting a logical one (digital receive interface pulse (analog receive interface) with an amplitude more than Q dB (defined by LIM1.RIL(2:0)) of the nominal pulse. The value in the ...
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RCLK 2.048 MHz/8 kHz or 1.544 MHz/8 kHz clock provided on pin SYNC (8 kHz in master mode only). The jitter attenuated DCO-R output clock can be output on pin RCLK ...
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LIM2.SCF for DCO-R, CMR6.SCFX for DCO-X ECFAX for DCO-X, ECFAR for DCO-R switches corner frequency to „Corner 0 frequency adjust“ Table sets corner frequency Reset Figure 23 Principle of Configuring the DCO-R ...
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Table 19 Clocking Modes of DCO-R Mode Internal LOS SYNC Input Active Master Independent Fixed to Master Independent 2.048 MHz (E1) or 1.544 MHz (T1) Master Independent 8.0 kHz Slave No Fixed to Slave No 2.048 MHz (E1) or 1.544 ...
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Figure 24 Jitter Attenuation Performance (E1 -10 -20 -30 -40 -50 -60 -70 1 Figure 25 Jitter Attenuation Performance (T1/J1) Also the requirements of ETSI TBR12/13 are ...
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UI 100 10 1 0.1 1 Figure 26 Jitter Tolerance (E1) 1000 UI 100 10 1 0.1 1 Figure 27 Jitter Tolerance (T1/J1) Data Sheet 10 100 1000 Jitter Frequency 10 100 1000 Jitter Frequency 67 OctalLIU PEF 22508 ...
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Output Jitter In the absence of any input jitter the OctalLIU theTable 20 below. Table 20 Output Jitter (E1) Specification Lower Cutoff ITU-T I.431 20 Hz 700 Hz ETSI TBR PUB 62411 ...
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In “one frame” or short buffer mode the delay through the receive buffer is reduced to an average delay of 128 or 46 bits. In bypass mode the time slot assigner is disabled. Slips are performed in all buffer modes ...
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Table 22 Summary of Alarm Detection and Release Alarm Detection Condition Loss-Of-Signal No transitions (logical zeros (LOS) programmable time interval 4096 consecutive pulse periods. Programmable receive input signal threshold Transmit Line Short More than 3 ...
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Transmit Path The transmit path of the OctalLIU XL3 XL1/XOID XL2 XL4 Transmit Line Interface XCLK Master MCLK Clocking Unit E: controlled by CMR2.IXSC and CMR2.IRSC F: controlled by CMR1.DXSS and automatic transmit clock switching G: controlled by LIM1.RL,JATT ...
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XL3 XL1 XL2 XL4 Figure 30 Transmit Line Interface Table 23 Recommended Transmitter Configuration Values R (Ohm), accuracy +/- 1 Application Mode SER % 1) 2 Generic 2 7.5 Non generic 2 1) The values in this column refers to ...
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TCLK is automatically performed if CMR6.ATCS = ´1´. All switchings of XCLK between TCLK and the DCO- X output are shown in the interrupt status bit ISR7.XCLKSS0 which is masked by IMR7.XCLKSS0. These kinds of switching cannot be done ...
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RL1/ROID Equalizer RL2 Receive Line Interface XL3 XL1/XOID1 XL2 XL4 Transmit Line Interface XCLK Master MCLK Clocking Unit Figure 31 Clocking and Data in Remote Loop Configuration 3.9.5 Dual Transmit Elastic Buffer The received single rail bit stream from pin ...
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By the registers XMP(2:0) compatible to the QuadLIU XPM2.XPDIS is cleared, see • the registers TXP(16:1), see TXP1, if the register bit XPM2.XPDIS is set, see For more details see chapter “Operational Description” To reduce the crosstalk ...
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Table 24 Recommended Pulse Shaper Programming for T1/J1 with Registers XPM(2:0) (Compatible to QuadLIU (cont’d)) LBO Range 0 122 to 162 0 162 to 200 7.5 --- 15 --- 22.5 --- Table 25 Recommended Pulse Shaper Programming for E1 with ...
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Table 27 Recommended Pulse Shaper Programming for E1 with registers TXP(16: Transmit TXP values, decimal SER 0 Line Interface Mode ( ) ( ) 120 Generic 42 7.5 120 Non generic Generic ...
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Framer Interface The framer interface of the OctalLIU Receive System (see chapter 3.6) Dual Receive Elastic Buffer recovered clock from J DCO-R Dual Transmit Eastic Buffer Transmit System (see chapter 3.8.) J: controlled by CMR2.IRSC and DIC1.RBS(1:0) K: controlled ...
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By the FCLKR input pin. In that case FCLKR input pin function must be selected by PC5.CSRP = ´0´ to use the receiver clock from the framer. In single rail mode of the transmit direction (LIM3.DRX = ´0´, LIM3), ...
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ISR3.SEC interrupt. In case PRBSSTA.PRS(2:1) is unequal ´11 interrupt mask bits should be cleared to return to normal operation. Because every bit error in the PRBS sequence increments the bit error counter BEC, no ...
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If a remote loop is activated by an automatic loop switching the register bit LIM0.JATT controls also if the jitter attenuator is active or not, see also If ALS.LILS is set (ALS), the remote loop is activated after an activation ...
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Local Loop The local loop-back is activated by • The control bit LIM0.LL (LIM0). • After detection of the appropriate In-band loop code, if enabled by ALS.SILS, see The local loop-back mode disconnects the receive lines RL1/2 or ROID ...
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Equalizer RL1/ROID RL2 Receive Line Interface Payload Loop XL3 XL1 XL2 XL4 Transmit Line Interface Figure 38 Payload Loop 3.11.6 Alarm Simulation Alarm simulation does not affect the normal operation of the device. However, possible not reported to the micro ...
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If a port is configured as GPOH or GPOL the port level is set fix to high or low-level respectively. Each of the input functions may only be selected once in a channel except for the GPI functionality. No input ...
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Register Description To maintain easy readability this chapter is divided into separate control register and status register sections. The higher address part of all global registers is ´00 number and is marked in the following tables ...
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Detailed Register Description Table 30 Registers Address Space Module Base Address Channel xx xx00 H Table 31 Registers Overview Register Short Name Register Long Name CMDR Command Register IMR1 Interrupt Mask Register 1 MR0 Mode Register 0 MR1 Mode ...
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Table 31 Registers Overview (cont’d) Register Short Name Register Long Name TXP1 TX Pulse Template Register 1 ALS Automatic Loop Switching Register IMR7 Interrupt Mask Register 7 LIM3 LIU Mode Register 3 RBD Receive Buffer Delay RES Receive Equalizer Status ...
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Table 31 Registers Overview (cont’d) Register Short Name Register Long Name TXP12 TX Pulse Template Register 12 TXP13 TX Pulse Template Register 13 TXP14 TX Pulse Template Register 14 TXP15 TX Pulse Template Register 15 TXP16 TX Pulse Template Register ...
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Table 32 Registers Access Types Mode Symbol Description Hardware (HW) Basic Access Types read/write rw Register is used as input for the HW read/write rwv Physically, there is no new register in virtual the generated register file. The real readable ...
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Control Registers Command Register CMDR Command Register Field Bits Type RRES 6 w XRES 4 w Interrupt Port Configuration See Chapter 3.5.3 and Table 9. IPC Interrupt Port Configuration Field Bits Type VISPLL 7 rw Data Sheet Register DescriptionCommand ...
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Field Bits Type SSYF 1:0 rw Interrupt Mask Register 1 Each interrupt source can generate an interrupt signal on port INT (characteristics of the output stage are defined by register IPC). A “1” bit position ...
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Similar Registers The other Interrupt Mask Registers have the same description. The Offset Addresses are listed in Table 33 IMRn Overview Register Short Name Register Long Name IMR2 Interrupt Mask Register 2 IMR3 Interrupt Mask Register 3 IMR4 Interrupt Mask ...
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Mode Register 0 MR0 Mode Register 0 Field Bits Type XC 7 5:4 rw EXZE 3 rw Data Sheet Offset xx1C H Description Transmit Code Serial line code for the transmitter, independent of the receiver. After changing XC(1:0), ...
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Field Bits Type ALM 2 rw SIM 0 rw Data Sheet Description Alarm Mode, E1 only Selects the AIS alarm detection mode in E1 mode. In T1/J1 mode this bit is reserved The AIS alarm is detected according ...
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Mode Register 1 MR1 Mode Register 1 Field Bits Type PMOD 4 rw XAIS 0 rw Mode Register 2 MR2 Mode Register 2 Field Bits Type RTM 5 rw DAIS 4 rw Data Sheet Offset xx1D H Description PCM Mode ...
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Field Bits Type PLB 2 rw Loop-Back Register LOOP Loop-Back Register Field Bits Type RTM 6 rw Data Sheet Register DescriptionLoop-Back Register Description Payload Loop-Back See Chapter 3.11. Normal operation. Payload loop is disabled The ...
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Mode Register 4 MR4 Mode Register 4 Field Bits Type Mode Register 5 MR5 Mode Register 5 Field Bits Type XLD/TT0 5 rw Data Sheet Offset xx20 H Description Transparent Mode, T1 only For T1/J1 mode this ...
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Field Bits Type XLU 4 rw XTM 2 rw Receive Control 0 RC0 Receive Control 0 Field Bits Type RDIS 3 rw Data Sheet Register DescriptionReceive Control 0 Description Transmit LLB Up Code, T1/J1 only This bit is not valid ...
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Transmit Pulse Mask 0 See Chapter 3.9.6.1 and Chapter pins XL1 and XL2. The level of the pulse shape can be programmed by registers XPM(2:0) if XPM2.XPDIS is set to ´0´ to create a custom waveform. If XPM2.XPDIS is set ...
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Transmit Pulse Mask 1 For description see Transmit Pulse Mask 0 XPM1 Transmit Pulse Mask1 Field Bits Type XP30 7 rw XP24 6 rw XP23 5 rw XP22 4 rw XP21 3 rw XP20 2 rw XP14 1 rw XP13 ...
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Field Bits Type DAXLT 5 rw XPDIS 4 rw XP34 3 rw XP33 2 rw XP32 1 rw XP31 0 rw Clear Channel Register 1 The registers CCB(1:3) are only valid in T1/J1 mode. CCB1 Clear Channel Register 1 Field ...
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Similar Registers Registers CCB2 and CCB3 have the same description. The Offset Addresses are listed in Table 35 CCBn Overview Register Short Name Register Long Name CCB2 Clear Channel Register 2 CCB3 Clear Channel Register 3 Table 36 Clear Channel ...
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Field Bits Type CMI 3 rw Line Interface Mode 0 LIM0 Line Interface Mode 0 Field Bits Type XFB 7 rw XDOS 6 rw RTRS 5 rw Data Sheet Register DescriptionLine Interface Mode 0 Description Select CMI Precoding, E1 only ...
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Field Bits Type DCIM 4 rw RLM MAS 0 rw Data Sheet Register DescriptionLine Interface Mode 0 Description Digital Clock Interface Mode Note: DCO-X must be used in DCIM mode (CMR1.DXJA = ´0´). 0 , ...
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Line Interface Mode 1 LIM1 Line Interface Mode 1 Field Bits Type CLOS 7 rw RIL2 6 rw RIL1 5 rw RIL0 4 rw JATT DRS 0 rw Data Sheet Register DescriptionLine Interface Mode 1 ...
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Pulse Count Detection Register PCD Pulse Count Detection Register Field Bits Type PCD 7:0 rw Pulse Count Recovery PCR Pulse Count Recovery Field Bits Type PCR 7:0 rw Data Sheet Register DescriptionPulse Count Detection Register Offset xx38 H Description Pulse ...
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Line Interface Mode 2 LIM2 Line Interface Mode 2 Field Bits Type SLT1 5 rw SLT0 4 rw SCF 3 rw ELT 2 rw Data Sheet Register DescriptionLine Interface Mode 2 Offset xx3A H Description Receive Slicer Threshold 00 , ...
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Loop Code Register 1 LCR1 Loop Code Register 1 Field Bits Type EPRM 7 rw XPRBS 6 rw LDC 5:4 rw LAC 3:2 rw FLLB 1 rw LLBP 0 rw Data Sheet Register DescriptionLoop Code Register 1 Offset xx3B H ...
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Table 37 FLLB Constant Values (Case 1) Name and Description Framed Line Loop-Back/Invert PRBS The line loop-back code is transmitted including framing bits. LLB code overwrites the FS/DL-bits. Framed Line Loop-Back/Invert PRBS The line loop-back code is transmitted unframed. LLB ...
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Loop Code Register 2 LCR2 Loop Code Register 2 Field Bits Type LDC 7:0 rw Loop Code Register 3 LCR3 Loop Code Register 3 Field Bits Type LAC 7:0 rw Data Sheet Register DescriptionLoop Code Register 2 Offset xx3C H ...
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Digital Interface Control 1 See Chapter 3.7.10. DIC1 Digital Interface Control 1 Field Bits Type RBS 5:4 rw BIM 2 rw XBS 1:0 rw Data Sheet Register DescriptionDigital Interface Control 1 Offset xx3E H Description Receive Buffer Size See Table ...
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Digital Interface Control 2 DIC2 Digital Interface Control 2 Field Bits Type CRB 5 rw Digital Interface Control 3 DIC3 Digital Interface Control 3 Field Bits Type CMI 7 rw Data Sheet Register DescriptionDigital Interface Control 2 Offset xx3F H ...
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Field Bits Type RRTRI 6 rw RTRI 5 FSCT 4 rw RESX 3 rw RESR 2 rw Data Sheet Register DescriptionDigital Interface Control 3 Description RDO Tristate Mode See Chapter 3.7.4 Note: RRTRI is logically exored with RTDMT multi function ...
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Clock Mode Register 4 CMR4 Clock Mode Register 4 Field Bits Type IAR 7 2:0 rw Data Sheet Register DescriptionClock Mode Register 4 Offset xx41 H Description Integral parameter selection (Corner frequency and attenuation selection) for the DCO-R ...
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Clock Mode Register 5 CMR5 Clock Mode Register 5 Field Bits Type DRSS 7:5 rw IAX 4:0 rw Data Sheet Register DescriptionClock Mode Register 5 Offset xx42 H Description DCO-R Channel Selection See Chapter 3.7. 000 , Receive reference clock ...
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Clock Mode Register 6 CMR6 Clock Mode Register 6 Field Bits Type DCOCOMPN 7 rw SRESR 6 rw SRESX 5 rw STF 4:2 rw Data Sheet Register DescriptionClock Mode Register 6 Offset xx43 H Description Compatibility programming of DCO-R/DCO-X disable ...
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Field Bits Type SCFX 1 rw ATCS 0 rw Clock Mode Register 1 CMR1 Clock Mode Register 1 Field Bits Type DCS 3 rw DXJA 1 rw Data Sheet Register DescriptionClock Mode Register 1 Description Select Corner Frequency of DCO-X ...
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Field Bits Type DXSS 0 rw Clock Mode Register 2 CMR2 Clock Mode Register 2 Field Bits Type ECFAX 7 rw ECFAR 6 rw DCOXC 5 rw Data Sheet Register DescriptionClock Mode Register 2 Description DCO-X Synchronization Clock Source 0 ...
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Field Bits Type DCF 4 rw IRSP 3 rw IRSC 2 rw IXSC 0 rw Data Sheet Register DescriptionClock Mode Register 2 Description DCO-R Center- Frequency Disabled See also Table 19 The DCO-R circuitry is frequency centered in ...
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Global Configuration Register GCR Global Configuration Register Field Bits Type VIS 7 rw SCI Data Sheet Register DescriptionGlobal Configuration Register Offset 0046 H Description Masked Interrupts Visible See also Chapter 3.5 Masked interrupt ...
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Clock Mode Register 3 CMR3 Clock Mode Register 3 Field Bits Type CFAX 7:4 rw CFAR 3:0 rw Port Configuration 1 See Chapter 3.12. PC1 Port Configuration 1 Field Bits Type RPC1 7:4 rw Data Sheet Register DescriptionClock Mode Register ...
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Field Bits Type XPC1 3:0 rw Table 41 RPC1 Constant Values Name and Description reserved reserved reserved reserved reserved reserved reserved reserved RLT: Receive line termination (input) “Hardware” switching of receive line termination, see GPI: general purpose input Value of ...
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Table 42 XPC1 Constant Values (cont’d) Name and Description TCLK: Transmit Clock (Input) A 2.048/8.192 MHz clock has to be sourced by the system if the internal generated transmit clock (DCO-X) is not used. Optionally this input is used as ...
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Port Configuration 5 PC5 Port Configuration 5 Field Bits Type PHDSX 7 rw PHDSR CSRP 1 rw CRP 0 rw Data Sheet Register DescriptionPort Configuration 5 Offset xx84 H Description Phase Decoder Switch for DCO-X ...
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Global Port Configuration 1 GPC1 Global Port Configuration 1 Field Bits Type CSFP 6:5 rw Port Configuration 6 PC6 Port Configuration 6 Field Bits Type TSRE 6 rw Data Sheet Register DescriptionGlobal Port Configuration 1 Offset 0085 H Description Configure ...
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Global Port Configuration Register 2 GPC2 Global Port Configuration Register 2 Field Bits Type FSS 6:4 rw R1S 2:0 rw Data Sheet Register DescriptionGlobal Port Configuration Register 2 Offset 008A H Description FSC Source Selection See Chapter 3.8.4. 000 , ...
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Global Clock Mode Register 1 GCM1 Global Clock Mode Register 1 Field Bits Type PHD_E1 7:0 rw Global Clock Mode Register 2 GCM2 Global Clock Mode Register 2 Field Bits Type PHSDEM 7 rw PHSDIR 6 rw PHSDS 5 rw ...
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Field Bits Type VFREQ_EN 4 rw PHD_E1 3:0 rw Data Sheet Register DescriptionGlobal Clock Mode Register 2 Description Variable Frequency Enable If “fixed mode” mode is selected the clock frequency at the pin MCLK must be 2.048 for E1 or ...
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Global Clock Mode Register 3 GCM3 Global Clock Mode Register 3 Field Bits Type PHD_T1 7:0 rw Global Clock Mode Register 4 GCM4 Global Clock Mode Register 4 Field Bits Type DVM_T1 7:5 rw Data Sheet Register DescriptionGlobal Clock Mode ...
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Field Bits Type PHD_T1 3:0 rw Global Clock Mode Register 5 GCM5 Global Clock Mode Register 5 Field Bits Type MCLK_LOW 7 rw PLL_M 4:0 rw Data Sheet Register DescriptionGlobal Clock Mode Register 5 Description Frequency Adjust for T1 (highest ...
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Global Clock Mode Register 6 GCM6 Global Clock Mode Register 6 Field Bits Type PLL_N 4:0 rw Flexible Clock Mode Settings If “flexible master clock mode” is used (VFREQ_EN = ´1´), the according register settings can be calculated as follows ...
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To bring the “characteristic T1 frequency” necessary: PHD_T1 = round (12288 x { [PHSN_T1 + (PHSX_T1 / 6 Example: = 2.048 MHz MCLK f PLL_N = 33; PLL_M = 278.528 MHz PLL f PHSN_E1 ...
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Global Clock Mode Register 7 GCM8 Global Clock Mode Register 7 Field Bits Type PHSX_T1 6:4 rw PHSN_T1 3:0 rw Global Interrupt Mask Register GIMR Global Interrupt Mask Register Field Bits Type PLLL 0 rw Data Sheet ...
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Test Pattern Control Register 0 See Chapter 3.11.1. TPC0 Test Pattern Control Register 0 Field Bits Type PRP 5 Pulse Template Register 1 See Chapter 3.9.6.1 and Chapter transmit pulse. The contents of this register is ignored unless ...
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Table 46 TXP Overview Register Short Name Register Long Name TXP2 TX Pulse Template Register 2 TXP3 TX Pulse Template Register 3 TXP4 TX Pulse Template Register 4 TXP5 TX Pulse Template Register 5 TXP6 TX Pulse Template Register 6 ...
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Field Bits Type R2S 2:0 rw Global Port Configuration Register 4 See Chapter 3.7. GPC4 Global Port Configuration Register 4 Field Bits Type R5S 6:4 rw R4S 2:0 rw Data Sheet Register DescriptionGlobal Port Configuration Register 4 Description RCLK2 Source ...
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Global Port Configuration Register 5 See Chapter 3.7. GPC5 Global Port Configuration Register 5 Field Bits Type R7S 6:4 rw R6S 2:0 rw Data Sheet Register DescriptionGlobal Port Configuration Register 5 Offset 00D5 H Description RCLK7 Source Selection 000 , ...
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Global Port Configuration Register 6 See Chapter 3.7. GPC6 Global Port Configuration Register 6 Field Bits Type R8S 2:0 rw In-Band Loop Detection Time Register INBLDTR In-Band Loop Detection Time Register Field Bits Type INBLDR 5:4 rw Data Sheet Register ...
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Automatic Loop Switching Register Enabling of automatic loop switching by In-band loop codes, see ALS Automatic Loop Switching Register Field Bits Type LILS 0 rw Interrupt Mask Register 7 Masks interrupt bits of register ISR7. IMR7 Interrupt Mask Register 7 ...
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LIU Mode Register 3 LIM3 LIU Mode Register 3 Field Bits Type DRR 1 rw DRX 0 rw 4.1.2 Status Registers Receive Buffer Delay RBD Receive Buffer Delay Field Bits Type RBD 5:0 r Data Sheet Register DescriptionLIU Mode Register ...
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Version Status Register VSTR Version Status Register Field Bits Type VSTR 7:0 r Receive Equalizer Status RES Receive Equalizer Status Field Bits Type EV 7:6 r RES 4:0 r Data Sheet Register DescriptionVersion Status Register Offset 004A H Description Version ...
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Line Status Register 0 LSR0 Line Status Register 0 Field Bits Type LOS 7 r AIS 6 r Data Sheet Register DescriptionLine Status Register 0 Offset xx4C H Description Loss-of-Signal • Detection: This bit is set when the incoming signal ...
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Line Status Register 1 LSR1 Line Status Register 1 Field Bits Type EXZD 7 r PDEN 6 r LLBDD 4 r LLBAD 3 r Data Sheet Register DescriptionLine Status Register 1 Offset xx4D H Description Excessive Zeros Detected Significant only, ...
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Field Bits Type XLS 1 r XLO 0 r Line Status Register 3 LSR3 Line Status Register 3 Field Bits Type ESC 7:5 r Data Sheet Register DescriptionLine Status Register 3 Description Transmit Line Short See Chapter 3.9.7. Significant only ...
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Table 47 Alarm Simulation States Tested Alarms ESC(2:0) = LFA LMFA RRA (bit2 = 0) RRA (S-bit frame 12) RRA (DL-pattern) 1) LOS 2) EBC (F12,F72) 2) EBC (only ESF) 1) AIS 2) FEC CVC CEC (only ESF) RSP RSN ...
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Line Status Register 2 LSR2 Line Status Register 2 Field Bits Type LLBDD 4 r LLBAD 3 r Data Sheet Register DescriptionLine Status Register 2 Offset xx4F H Description Line Loop-Back Deactivation Signal Detected, only valid in E1 mode In ...
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Code Violation Counter Lower Byte CVCL Code Violation Counter Lower Byte Field Bits Type CV7 7 r CV6 6 r CV5 5 r CV4 4 r CV3 3 r CV2 2 r CV1 1 r CV0 0 r Data Sheet ...
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Code Violation Counter Higher Byte CVCH Code Violation Counter Higher Byte Field Bits Type CV15 7 r CV14 6 r CV13 5 r CV12 4 r CV11 3 r CV10 2 r CV9 1 r CV8 0 r Data Sheet ...
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PRBS Bit Error Counter Lower Bytes BECL PRBS Bit Error Counter Lower Bytes Field Bits Type BEC7 7 r BEC6 6 r BEC5 5 r BEC4 4 r BEC3 3 r BEC2 2 r BEC1 1 r BEC0 0 r ...
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PRBS Bit Error Counter Higher Bytes BECH PRBS Bit Error Counter Higher Bytes Field Bits Type BEC15 7 r BEC14 6 r BEC13 5 r BEC12 4 r BEC11 3 r BEC10 2 r BEC9 1 r BEC8 0 r ...
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Interrupt Status Register 1 All bits are reset when ISR1 is read. If bit GCR.VIS is set, interrupt statuses in ISR1 are flagged although they are masked by register IMR1. However, these masked interrupt statuses neither generate a signal on ...
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Interrupt Status Register 2 All bits are reset when ISR2 is read. If bit GCR.VIS is set, interrupt statuses in ISR2 are flagged although they are masked by register IMR2. However, these masked interrupt statuses neither generate a signal on ...
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Field Bits Type LLBSC 3 rsc RSN 1 rsc RSP 0 rcs Interrupt Status Register 4 All bits are reset when ISR4 is read. If bit GCR.VIS is set, interrupt statuses in ISR4 are flagged although they are masked by ...
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Field Bits Type XSN 6 rsc Global Interrupt Status Register This status register points to pending interrupts sourced by ISR(1:4) and ISR(6:7), see GIS Global Interrupt Status Register Field Bits Type ISR7 7 rsc ISR6 6 rsc ISR5 5 rsc ...
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Channel Interrupt Status Register This status register points to pending interrupts of channels 1to 8, see CIS Channel Interrupt Status Register Field Bits Type GIS8 7 rsc GIS7 6 rsc GIS6 5 rsc GIS5 4 rsc GIS4 3 rsc GIS3 ...
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Multi Function Port Input Register This register always reflects the state of the multi function ports, see according port should be switched to general purpose input mode. If not, the programmed output signal can be monitored through this register (see ...
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Interrupt Status Register 6 ISR6 Interrupt Status Register 6 Field Bits Type LILSU 1 rsc LILSD 0 rsc Global Interrupt Status 2 Interrupt status register for the PLL of the master clocking unit. GIS2 Global Interrupt Status 2 Field Bits ...
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Field Bits Type PLLLC 0 rsc Interrupt Status Register 7 All bits are reset when ISR7 is read. If bit GCR.VIS is set, interrupt statuses in ISR7 are flagged although they are masked by register IMR7. However, these masked interrupt ...
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PRBS Status Register PRBSSTA PRBS Status Register Field Bits Type PRS 2:0 r Data Sheet Register DescriptionPRBS Status Register Offset xxDA H Description PRBS Status Information Note: Every change of the bits PRS sets the interrupt bit ISR1.LLBSC if register ...
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Clock Status Register The bits show the current status of the input clocks TCLK and FCLKX. CLKSTAT Clock Status Register Field Bits Type TCLKLOS 4 r FCLKXLOS 3 r Data Sheet Register DescriptionClock Status Register Offset xxFE H Description Loss ...
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Package Outlines Figure 39 shows the package outline. A16 C Figure 39 PG-LBGA-256-1 (Plastic Low Profile Ball Grid Array Package), SMD Dimensions in mm Note: The upper drawing shows the “Bottom View” of the package. Data Sheet 15 x ...
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Electrical Characteristics In Table 48 the absolute maximum ratings of the OctalLIUTM are listed. Table 48 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Moisture Level 3 temperature IC supply voltage (pads, digital) IC supply voltage (core, ...
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Table 49 Operating Range Parameter Ambient temperature Supply voltage digital pads Supply voltage digital core Supply voltage analog receiver Supply voltage analog transmitter Analog input voltages Digital input voltages Ground 1) Voltage ripple on analog supply less than 50 mV ...
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Table 50 DC Characteristics (cont’d) Parameter Input leakage current Input pullup current Output leakage current Transmitter leakage current Transmitter output impedance Transmitter output current Differential peak voltage of a mark (between XL1 and XL2) Receiver peak voltage of a mark ...
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Table 50 DC Characteristics (cont’d) Parameter Loss-Of-signal (LOS) detection limit 1) Applies to all input pins except analog pins RLx 2) Applies to all output pins except pins XLx 3) Wiring conditions and external circuit configuration according to 4) Pin ...
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AC Characteristics 6.1.1 Master Clock Timing Figure 40 shows the timing and MCLK. The accuracy is required to fulfill the jitter requirements, see MCLK Figure 40 MCLK Timing Table 51 MCLK Timing Parameter Values Parameter Clock period of MCLK ...
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JTAG Boundary Scan Interface Figure 41 shows the timing and boundary scan test of the OctalLIUTM, see TRS TCK TMS, TDI TDATI TDO, TDATO Figure 41 JTAG Boundary Scan Timing Table 52 JTAG Boundary Scan Timing Parameter Values Parameter ...
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Reset Figure 42 shows the timing and Table 53 of the OctalLIUTM. Figure 42 Reset Timing Table 53 Reset Timing Parameter Value Parameter RES pulse width low 1) While MCLK is running 6.1.4 Asynchronous Microprocessor Interface 6.1.4.1 Intel Bus ...
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Ax BHE ALE Figure 44 Intel Multiplexed Address Timing READY Figure 45 Intel Read Cycle Timing Data Sheet 169 ...
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READY Figure 46 Intel Write Cycle Timing Table 54 Intel Bus Interface Timing Parameter Values Parameter Address, BHE setup time Address, BHE hold time CS setup time CS hold time Address, BHE stable before ALE ...
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Motorola Bus Interface Mode Figure 47 and Figure 48 show the timing of the SCI Interface and values. Ax, BLE DTACK Figure 47 Motorola Read Cycle Timing Ax, BLE DTACK Figure ...
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Table 55 Motorola Bus Interface Timing Parameter Values Parameter Address, BLE setup time before DS active Address, BLE hold after DS inactive CS active before DS active CS hold after DS inactive RW stable before DS active RW hold after ...
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Table 56 SCI Timing Parameter Values Parameter SCI_CLK cycle time in full duplex mode 1 SCI_CLK cycle time in half duplex mode 1 SCI_CLK clock low time SCI_CLK clock high time SCI_RXD setup time before SCI_CLK SCI_RXD hold time after ...
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Digital Interface (Framer Interface) Figure 51, Figure 52, Figure 53 appropriate timing parameter values at the digital interface of the OctalLIUTM. FCLKX (TPE=0) FCLKX (TPE=1) XDI, XDIN Figure 51 FCLKX Output Timing Table 58 FCLKX Timing Parameter Values Parameter ...
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Table 59 FCLKR Timing Parameter Values Parameter FCLKR clock period E1 FCLKR clock period T1/J1 FCLKR high FCLKR low RDO, RDON delay SYNC Figure 53 SYNC Timing Table 60 SYNC Timing Parameter Values Parameter SYNC high time SYNC low time ...
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Pulse Templates - Transmitter The transmitter includes a programmable pulse shaper to generate transmit pulse masks according to: • For T1: FCC68; ANSI T1. 403 1999, figure 4; ITU-T G703 11/2001, figure 10 (for different cable lengths), see Figure ...
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Figure 56 T1 Pulse Shape at the Cross Connect Point Table 62 T1 Pulse Template at Cross Connect Point (T1.102 Maximum Curve Time [ns] Level [%] 0 5 250 5 325 80 325 115 425 115 500 105 675 105 ...
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Package Characteristics The following table shows the thermal characteristics of the BGA package together with different PCBs. Table 64 Package Characteristic Values Parameter Thermal Resistance between junction and PCB for BGA 256 package Junction Temperature 6.4 Test Configuration 6.4.1 ...
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Power Supply Test For power supply test all eight channels of the OctalLIUTM are active. Transmitter and receiver are configured as for typical applications. The transmitted data are looped back to the receiver by a short line as shown ...
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Table 67 Power Supply Test Conditions T1/J1 Parameter Load Resistance Termination Resistance Line Impedance Line Length Transformer Ratio Transmit Transformer Ratio Receive Framer interface Frequency Test SignalActive Channels (DCOs active, 2-frame buffer)4 Pulse Mask Programming (compatible to QuadLIU®) Ambient Temperature ...
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Operational Description 7.1 Operational Overview Every of the eight channels of the OctalLIU T1/J1 mode, selected by the register bit GCM2.VFREQ_EN, see • In the so called “flexible master clocking mode” (GCM2.VFREQ_EN = ´1´) all eight ports can work ...
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Device Initialization TM After reset, the OctalLIU is initialized for E1 with register values listed in the following table. Table 68 Initial Values after Reset Register Reset Value LIM0, LIM1, ´00 ´, ´00 ´ PCD, PCR ´00 ...
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Table 69 Configuration Parameters (E1) Basic Set Up Master clocking mode E1 mode select Clock system configuration Specification of line interface Specification of transmit pulse mask Line interface coding Loss-of-signal detection/recovery conditions Multi Function Port selection Features like alarm simulation ...
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PCM line starts. Such procedures are specified in ITU-T recommendations (e.g. fault conditions and consequent actions). Setting optional parameters primarily makes sense when basic operation via the PCM line is guaranteed. ...
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Table 72 Line Interface Configuration (T1/J1) Register Function PCR = ´15 ´ LOS recovery after 22 “ones” in the PCD interval (fulfills G.775, Bellcore/AT&T). H LIM1.RIL(2:0) = ´02 ´ LOS threshold of 0.6 V (fulfills G.775). H GCR.SCI = ´1´ ...
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Device Configuration for Digital Clock Interface Mode (DCIM) The following table shows the necessary configuration for the Digital Clock Interface Mode (DCIM), see ITU-T G.703 11/2001, chapter 13. The receive clock at RL1/RL2 (2.048 MHz) is supported at multi ...
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Appendix 8.1 Protection Circuitry The design in Figure 59 shows an example of how to build up a generic E1/T1/J1 platform. The circuit shown has been successfully checked against ITU-T K.20 and K.21 lightning surge tests (basic level). RL1 ...
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Figure 60 Screen Shot of the “Master Clock Frequency Calculator” Data Sheet 188 TM OctalLIU PEF 22508 E Appendix F0126 Rev. 1.0, 2005-06-02 ...
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Figure 61 Screen Shot of the “External Line Frontend Calculator” Data Sheet 189 TM OctalLIU PEF 22508 E Appendix F0198_2256 Rev. 1.0, 2005-06-02 ...
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Terminology A A/D Analog to digital ADC Analog to Digital Converter AIS Alarm Indication Signal (blue alarm) AGC Automatic Gain Control ALOS Analog Loss Of Signal AMI Alternate Mark Inversion ANSI American National Standards Institute ATM Asynchronous Transfer Mode AUXP ...
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GIS Global Interrupt Status H HBM Human body model for ESD classification HDB3 High density bipolar of order 3 I IBIS I/O buffer information specification (ANSI/EIA-656) IBL In Band Loop ISDN Integrated Services Digital Network ITU International Telecommunications Group J ...
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RX Receiver S SAPI Service Access Point Identifier (special octet in PPR) SCI Serial ControlInterface SPI Serial Peripheral Interface Sidactor Overvoltage protection device for transmission lines T TAP Test Access Port TEI Terminal Endpoint Identifier (special octet in PPR) TX ...
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