PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 128

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Field
VFREQ_EN
PHD_E1
Data Sheet
Bits
4
3:0
Type
rw
rw
Description
Variable Frequency Enable
If “fixed mode” mode is selected the clock frequency at the pin MCLK
must be 2.048 for E1 or 1.544 MHz for T1/J1 respectively. The setting of
the whole clock mode is done automatically: Register bits of GCM1,
GCM2.PHSDEM, PHDIR, PHSDS, PHD_E1 and GCM3 to GCM8 are
unused. If “fixed mode” mode is selected and the SPI- or SCI-interface is
used as controller interface, the pinstrapping values at D(15:5) are also
not used. See also
Note: If “fixed mode “ is enabled all of the eight ports must work in the
0
1
Frequency Adjust for E1
(highest 4 bits, for lower 8 bits see GCM1)
The 12 bit frequency adjust value is in the decimal range of -2048 to
+2047. Negative values are represented in 2s-complement format. For
details see calculation formulas in register
100000000000
.......................
000000000000
......................
011111111111
B
B
same mode, either in T1 or in E1 mode. A switching between E1
and T1 modes causes a reset of the whole clock system. If “fixed
mode“ is disabled a switching between E1 and T1 mode (which can
be done in this case individually for every port) causes not a reset
of the whole clock system.
, Fixed clock frequency of 2.048 (E1) or 1.544 MHz (T1/J1)
, Variable master clock frequency (normal operation, operation after
reset)
B
B
,
128
B
B
B
,
, -2048
, 0
, +2047
Register DescriptionGlobal Clock Mode Register 2
Chapter
3.5.5.
GCM6
and
Rev. 1.0, 2005-06-02
Table
PEF 22508 E
OctalLIU
45.
TM