PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 119

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Field
DCF
IRSP
IRSC
IXSC
Data Sheet
Bits
4
3
2
0
Type
rw
rw
rw
rw
Description
DCO-R Center- Frequency Disabled
See also
0
1
Internal Receive System Frame Sync Pulse
Note: Recommendation: This bit should be set to ´1´.
0
1
Internal Receive Digital (Framer) Clock
See also
0
1
Internal Transmit Digital (Framer) Clock
See also
0
1
B
B
B
B
B
B
B
B
, The DCO-R circuitry is frequency centered in master mode if no
2.048 MHz reference clock on pin SYNC is provided or in slave
mode if a loss-of-signal occurs in combination with no 2.048 MHz
clock on pin SYNC or a gapped clock is provided on pin RCLKI and
this clock is inactive or stopped.
, The center function of the DCO-R circuitry is disabled. The
generated clock (DCO-R) is frequency frozen in that moment when
no clock is available on pin SYNC or pin RCLKI. The DCO-R
circuitry starts synchronization as soon as a clock appears on pins
SYNC or RCLKI.
, The frame sync pulse is derived from RDOP output signal
internally (free running).
, The frame sync pulse for the receive system interface is internally
sourced by the DCO-R circuitry. This internally generated frame
sync signal can be output (active low) on multifunction ports RP(A
to D) (RPC(3:0) = ´0001
, The working clock for the receive framer interface is sourced by
FCLKR or in receive elastic buffer bypass mode from the
corresponding extracted receive clock RCLK.
, The working clock for the receive framer interface is sourced
internally by DCO-R or in bypass mode by the extracted receive
clock. FCLKR is ignored.
, The working clock for the transmit framer interface is sourced by
FCLKX.
, The working clock for the transmit framer interface is sourced
internally by the working clock of the receive framer interface.
FCLKX is ignored.
Table
Figure
Figure
119
19.
35.
35.
Register DescriptionClock Mode Register 2
H
´).
Rev. 1.0, 2005-06-02
PEF 22508 E
OctalLIU
TM