PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 30

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Table 1
Pin No. Ball
Data Sheet
No.
D2
E7
B1
D2
E7
B1
D2
E7
B1
D2
E7
B1
D2
E7
B1
D2
E7
B1
D2
E7
B1
D2
E7
B1
I/O Signals (cont’d)
Name
RPA1
RPB1
RPC1
RPA1
RPB1
RPC1
RPA1
RPB1
RPC1
RPA1
RPB1
RPC1
RPA1
RPB1
RPC1
RPA1
RPB1
RPC1
RPA1
RPB1
RPC1
RPA1
RPB1
RPC1
Pin Type Buffer
I/O
I/O
I/O
I
I
I
I
O
O
O
O
O
Type
PU/–
PU/–
PU/–
PU
PU
PU
PU
–
–
–
–
–
30
Function
Receive Multifunction Pins A to C, port 1
Depending on programming of bits PC(1:3).RPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the OctalLIU
reset these ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESR
latching/transmission of data is done with the rising or
falling edge of FCLKR. If not connected, an internal pull-
up transistor ensures a high input level.
An input function must not be selected twice or more.
Selectable pin functions are described below.
Receive Line Termination (RLT), port 1
PC(1:3).RPC(3:0) = ´1000
These input function controls together with LIM0.RTRS
the analog switch of the receive line interface: A logical
equivalence is build out of LIM0.RTRS and RLT.
General Purpose Input (GPI), port 1
PC(1:3).RPC(3:0) = ´1001
The pin is set to input. The state of this input is reflected
in the register bits MFPI.RPA, MFPI.RPB or MFPI.RPC
respectively.
General Purpose Output High (GPOH), port 1
PC(1:3).RPC(3:0) = ´1010
The pin level is set fix to high level.
General Purpose Output Low (GPOL), port 1
PC(1:3).RPC(3:0) = ´1011
The pin level is set fix to low level.
Loss of Signal Indication Output (LOS), port 1
PC(1:3).RPC(3:0) = ´1100
The output reflects the Loss of Signal status as readable
in LSR0.LOS.
Receive Data Output Negative (RDON), port 1
PC(1:3).RPC(3:0) = ´1110
Receive data output negative for dual rail mode on
digital (framer) interface (LIM3.DRR = ´1´).
Bipolar violation output for single rail mode on digital
(framer) interface (LIM3.DRR = ´0´).
Receive Clock Output (RCLK), port 1
PC(1:3).RPC(3:0) = ´1111
Receive clock output RCLK. After reset RCLK is
configured to be internally pulled up weekly. By setting
of PC5.CRP RCLK is an active output.
RCLK source and frequency selection is made by
CMR1.RS(1:0) if COMP = ´1´ or by CMR4.RS(2:0) if
COMP = ´0´.
b
b
b
b
b
b
b
´.
.
´.
´.
.
´.
´. Default setting after reset
Rev. 1.0, 2005-06-02
Pin Descriptions
PEF 22508 E
OctalLIU
TM
. After
TM