PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 98
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PEF 22508 E V1.1-G
Manufacturer Part Number
PEF 22508 E V1.1-G
Description
IC INTERFACE E1/T1/J1 LBGA-256
Manufacturer
Infineon Technologies
Series
OctalLIU™r
Datasheet
1.PEF_22508_E_V1.1.pdf
(193 pages)
Specifications of PEF 22508 E V1.1-G
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Current - Supply
370mA
Power (watts)
140mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-LSBGA
Includes
Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PEF22508EV1.1T
PEF22508EV11GXP
SP000029953
PEF22508EV11GXP
SP000029953
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Field
XLU
XTM
Receive Control 0
RC0
Receive Control 0
Field
RDIS
Data Sheet
Bits
4
2
Bits
3
Type
rw
rw
Type
rw
Description
Transmit LLB Up Code, T1/J1 only
This bit is not valid in E1 mode. The equivalent bit in E1 mode is
MR3.XLU.
0
1
Transmit Transparent Mode
For proper operation this bit must be set to ´1´.
Description
Receive Data Input Sense
Configures the input polarity of the digital receive inputs.
0
1
B
B
B
B
, Normal operation.
, A one in this bit position causes the transmitter to replace normal
transmit data with the LLB up (activate) code continuously until this
bit is reset. The LLB up code is optionally overwritten by the
framing/DL/CRC bits. For proper operation bit MR5.XLD must be
cleared.
, In dual rail mode RDI, RDIN are active low, in DCIM mode ROID
is active high.
, In dual rail mode RDI, RDIN are active high, in DCIM mode ROID
is active low.
Offset
xx24
98
H
Register DescriptionReceive Control 0
Rev. 1.0, 2005-06-02
PEF 22508 E
OctalLIU
Reset Value
00
TM
H
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