PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 42

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

3.4
Figure 5
Figure 5
3.5
The four possible micro controller interface modes - two asynchronous modes (Intel, Motorola) and two serial
interface modes (SPI bus or SCI bus) - are selected by using the interface mode selection pins IM(1:0). This
selection is valid immediately after reset becomes inactive.
After changing of the interface mode by IM(1:0), a hardware reset must be applied.
3.5.1
The asychronous micro controller interface is selected if IM(1:0) is strapped to ´00B´ (Intel mode) or ´01B´
(Motorola mode).
An handshake signal (data acknowledge DTACK for Motorola- and READY for Intel-mode) is provided indicating
successful read or write cycle. By using DTACK or READY respectively no counter is necessary in the micro
controller to finish the access, see also timing diagrams
The generation of READY is asynchronous:
In Intel mode read access READY will be set to low by the OctalLIU
OctalLIU
before it will be set to high by the OctalLIU
In the Intel mode write access READY will be set to low by the OctalLIU
driven by the micro controller). After WR is high and data are written successfully into the registers of the
OctalLIU
The general timing diagrams are shown in
Data Sheet
RL1/ROID(1:8)
XL1/XOID(1:8)
RLS(1:8)
RL2(1:8)
XL2(1:8)
XL3(1:8)
XL4(1:8)
TM
TM
shows the block diagram of the OctalLIU
. After the rising edge of RD (which is driven by the micro controller), READY is low for a “hold time”,
, READY will be set to high by the OctalLIU
Block Diagram
Block Diagram
Functional Blocks
Asynchronous Micro Controller Interface (Intel or Motorola mode)
IM(1:0)
TDI,TMS,TCK,TRS,TDO
Haul Receive
Line Interface
Clock & Data
Haul Transmit
Line Interface
Long+Short
Long+Short
Boundary Scan
Recovery
JTAG
A(10:0)
TM
Figure 43
CS
Asynchronous Micro
.
Controller Interface
WR/RW
Line Decoder
PRBS Monitor
Line Encoder
PRBS Gener.
IBL Generator
IBL Monitor
RD/DS
TM
BHE/BLE
.
to
TM
42
ALE
Figure
Figure 43
.
DBW
SCI Interface
RES
Jitter Attunator
48.
Receive
INT
Dual Receive
Elastic Buffer
Dual Transmit
Elastic Buffer
READY/TDACK
ff.
Jitter Attunator
Transmit
SPI Interface
TM
TM
after the data output is stable at the
D(15:0)
after the falling edge of WR (which is
MUX
MUX
MCLK SYNC FSC
Interface
Transmit
Interface
Receive
Framer
Framer
Master Clocking
Functional Description
Unit
TCLK
RCLK
Rev. 1.0, 2005-06-02
OctalLIU_blockdiagram
PEF 22508 E
OctalLIU
FCLKR(1:8)
RDO(1:8)
RPA(1:8)
RPB(1:8)
RPC(1:8)
XDI(1:8)
XPA(1:8)
XPB(1:8)
FCLKX(1:8)
TM