PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 144

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Field
XLS
XLO
Line Status Register 3
LSR3
Line Status Register 3
Field
ESC
Data Sheet
Bits
1
0
Bits
7:5
Type
r
r
Type
r
Description
Transmit Line Short
See
by LIM1.DRS = ´0´.
0
1
Transmit Line Open
See also
0
1
Description
Error Simulation Counter, T1 only
This three-bit counter is incremented by setting bit MR0.SIM. The state of
the counter determines the function to be tested. For complete checking
of the alarm indications, eight simulation steps are necessary (LSR3.ESC
= ´000
B
B
B
B
Chapter
, Normal operation. No short is detected.
, The XL1 and XL2 are shortened for at least 3 pulses. As a reaction
of the short the pins XL1 and XL2 are automatically forced into a
high-impedance state if bit XPM2.DAXLT is reset. After 128
consecutive pulse periods the outputs XL1/2 are activated again
and the internal transmit current limiter is checked. If a short
between XL1/2 is still further active the outputs XL1/2 are in high-
impedance state again. When the short disappears pins XL1/2 are
activated automatically and this bit is reset. With any change of this
bit an interrupt ISR1.XLSC is generated. In case of XPM2.XLT is
set this bit is frozen.
, Normal operation
, This bit is set if at least 32 consecutive zeros were sent on pins
XL1/XL2 or XDOP/XDON. This bit is reset with the first transmitted
pulse. With the rising edge of this bit an interrupt ISR1.XLSC is set.
In case of XPM2.XLT is set this bit is frozen.
b
´ after a complete simulation).
Chapter
Offset
xx4E
3.9.7. Significant only if the ternary line interface is selected
144
3.9.7.
H
Register DescriptionLine Status Register 3
Rev. 1.0, 2005-06-02
PEF 22508 E
OctalLIU
Reset Value
xx
TM
H