PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 28

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Table 1
Pin No. Ball
Digital (Framer) Interface Receive
Data Sheet
No.
J6
G13
G12
C2
C1
E4
E1
L6
K4
M3
M1
P15
P16
M10
M16
F15
I/O Signals (cont’d)
Name
MCLK
SYNC
FSC
RDO1
FCLKR1
RDO2
FCLKR2
RDO3
FCLKR3
RDO4
FCLKR4
RDO5
FCLKR5
RDO6
FCLKR6
RDO7
Pin Type Buffer
I
I
O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
Type
–
PU
–
–
PU
–
PU
–
PU
–
PU
–
PU
–
PU
–
28
Function
Master Clock
A reference clock of better than ±32 ppm accuracy in
the range of 1.02 to 20 MHz must be provided on this
pin. The OctalLIU
clocks from this master
(see registers GCM(6:1)).
Clock Synchronization of DCO-R
If a clock is detected on pin SYNC the
DCO-R circuitry of the OctalLIU
1.544/2.048 MHz clock (see LIM0.MAS, CMR1.DCS
and CMR2.DCF). Additionally, in master mode the
OctalLIU
clock (IPC.SSYF = ´1´). If not connected, an internal
pull-up transistor ensures high input level.
8 kHz Frame Synchronization
The optionally synchronization pulse is active high or
low for one 2.048/1.544 MHz cycle (pulse width =
488 ns for E1and 648 ns or T1/J1).
Receive Data Out, port 1
Received data at RL1, RL2 is sent to RDOP, RDON.
Clocking of data is done with the rising or falling edge of
RCLK.
Framer Data Clock Receive, port 1
Input if PC5.CSRP = ´0´, output if PC5.CSRP = ´1´.
Receive Data Out, port 2
See description of RDOP1.
Framer Data Clock Receive, port 2
See description of FCLKR1.
Receive Data Out, port 3
See description of RDOP1.
Framer Data Clock Receive, port 3
See description of FCLKR1.
Receive Data Out, port 4
See description of RDOP1.
Framer Data Clock Receive, port 4
See description of FCLKR1.
Receive Data Out, port 5
See description of RDOP1.
Framer Data Clock Receive, port 5
See description of FCLKR1.
Receive Data Out, port 6
See description of RDOP1.
Framer Data Clock Receive, port 6
See description of FCLKR1.
Receive Data Out, port 7
See description of RDOP1.
TM
is able to synchronize to an 8 kHz reference
TM
internally derives all necessary
TM
synchronizes to this
Rev. 1.0, 2005-06-02
Pin Descriptions
PEF 22508 E
OctalLIU
TM