PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 49

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Figure 12
is marked by the falling edge of the chip select signal CS whereas the end of the operations is marked by the rising
edge of CS. Because of CS the SPI interface has no slave address.
The first bit of the serial data in (SDI) is ´1´ for a read operation and ´0´ for a write operation. The first four bits of
the 15-bit address are not valid for the OctalLIU
In read operation the OctalLIU
(SDO).
In general SPI data are driven with the negative edge of the serial clock (SCLK) and sampled with the positive
edge of SCLK.
values.
Figure 12
Figure 13
3.5.3
Special events in the OctalLIU
micro controller to read status information from the OctalLIU
electrical characteristics (open drain or push-pull) is programmed defined by the register bits IPC.IC(1:0), see IPC.
The OctalLIU
defined by registers IPC) too.
Since only one INT request output is provided, the cause of an interrupt must be determined by the external micro
controller by reading the OctalLIU
pin INT and the interrupt status bits are reset by reading the interrupt status registers. The interrupt status registers
ISR are of type “clear on read“ (“rsc”).
The structure of the interrupt status registers is shown in
Data Sheet
and
SPI Read Operation
SPI Write Operation
Interrupt Interface
TM
Figure 13
Figure 50
SCLK
has a single interrupt output pin INT with programmable characteristics (open drain or push-pull,
SCLK
SDO
SDO
SDI
CS
SDI
CS
show the read and the write operation respectively. The start of a read or write operation
shows the timing of the SPI interface and
x
x
x
x
TM
TM
x
high impedance
x
high impedance
are indicated by means of an interrupt output INT, which requests the external
delivers the 8 bit wide content of the addressed register at the serial data out
x
TM
x
’s interrupt status registers (GIS, ISR(1:4), ISR6 and ISR7). The interrupt on
A10
A10
11 bit address
11 bit address
TM
.
49
Figure
A0
TM
A0 D7
, or to transfer data from/to the OctalLIU
D7
14.
don´t care
8 bit data
Table 57
8 bit data
the appropriate timing parameter
D0
O ctal_F ALC _SPI_read
O ctal_F ALC _SPI_w rite
D0
Functional Description
Rev. 1.0, 2005-06-02
PEF 22508 E
OctalLIU
TM
. The
TM