PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 46

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Figure 8
Every write into or read from a register of the OctalLIU
(micro con roller) and is then confirmed by an acknowledge message ACK from the OctalLIU
configuration automatic acknowledgement is set (bit ACK_EN, see
The frame structure of this messages are shown in
In general the LSB of every byte is transmitted first and lower bytes are transmitted before higher bytes (regarding
the register address)
Source and destination addresses are 8 bits long. Only the first 6 bits are really used for addressing. The bit C/R
(Command/Response) distinguishes between a command and a response. The bit MS (Master/Slave) is ´0
all Slaves and ´1
The source address is defined by pinstrapping of A5 to A0 after reset, but other values can be configured by
programming of the SCI configuration register.
The payload of the write CMD includes two control bits (MSBs of the payload), which distinguish between the
different kind of commands, see
CMD payload includes only the control bits and the register address. Register addresses can be either OctalLIU
register addresses or SCI configuration register addresses. Because of the address space of the OctalLIU
really 11 LSBs of the 14 bit address are used in the OctalLIU
The Frame Check Sequence FCS has16 bits
The Read Status Byte RSTA of the acknowledge message shows the status of the received message and is built
by the SCI interface of the OctalLIU
The destination address in the ACK message is always the source address of the corresponding CMD (the
address of the micro controller), see
interface
Data Sheet
SCI Message Structure of OctalLIU
B
´ for all masters, see
Table
TM
HOST
Figure
, see
7, the 14 bit wide register address and the 8 bit wide data whereas the read
Table 8
Figure 11
10, because no CMD messages will be sent by the OctalLIU
and
TM
CMD
ACK
Figure
Figure 9
and
TM
46
is initiated by a command message CMD from the Host
Table
9.
TM
OctalLIU
. The 3 MSBs are ignored
OctalLIU_SCI_message_structure
6.
Table
8).
Functional Description
Rev. 1.0, 2005-06-02
PEF 22508 E
TM
OctalLIU
if in the SCI
TM
B
´ for
SCI
TM
TM
TM
,