PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 71

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

3.9
The transmit path of the OctalLIU
Figure 29
The serial transmit bit stream (single rail or dual rail) is processed by the transmitter which has the following
functions:
•
•
3.9.1
The principle transmit line interface is shown in
•
•
In E1 mode the value of R
Shorts between XL1 and XL2 cannot be detected, see
The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the
appropriate programmable shape. The unipolar data is provided on pin XDI and the digital transmitter.
Data Sheet
Transmit Line
Interface
AIS generation (blue alarm)
Generation of In-band loop-up/-down code
For non-generic applications pins XL3 and XL4 can be left open. The serial resistance R
the operation mode (E1/T1/J1) as shown in
For generic E1/T1/J1 applications with optimized return loss the transmit output resistance is configured by
using the pins XL3 and XL4 as shown in
(register bit PC6.TSRE) without the need for external hardware changes: Here R
Table
XL1/XOID
MCLK
XCLK
XL3
XL2
XL4
23.
Transmit Path
Transmit System of one Channel
Transmit Line Interface
E: controlled by CMR2.IXSC and CMR2.IRSC
F: controlled by CMR1.DXSS and automatic transmit clock switching
G: controlled by LIM1.RL,JATT and LIM2.ELT
H: controlled by DIC1.XBS(1:0) and automatic transmit clock switching
%: divider: controlled by CMR6.STF(2:0)
Clocking Unit
Master
SER
in
Table 23
DAC
TM
is shown in
Shaper,
Pulse
LBO
is valid for both characteristic line impedances Z
Figure
Table
Figure
Figure
30. The operation mode (E1/T1/J1) is selected by software
23.
Chapter
71
30. Two application modes are possible:
29.
Encoder
3.9.7.
H
Dual Transmit Elastic Buffer
DCO-X
Automatic Transmit
Clock Switching
recovered
receive clock
G
Functional Description
0
SER
= 120
Rev. 1.0, 2005-06-02
F
SER
is always 2
internal
transmit
clock
O c talLIU _ITS 10305
PEF 22508 E
is dependent on
and Z
OctalLIU
%
E
from
DCO-R
0
= 75
FCLKX
XDIP
XDIN
FCLKR
TCLK
(in)
, see
TM
.