PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 95

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Mode Register 1
MR1
Mode Register 1
Field
PMOD
XAIS
Mode Register 2
MR2
Mode Register 2
Field
RTM
DAIS
Data Sheet
Bits
4
0
Bits
5
4
Type
rw
rw
Type
rw
rw
Description
PCM Mode
This bit decides between E1 and T1/J1 mode. Switching from E1 to T1 or
vice versa the device needs up to 20 s to settle up to the internal
clocking.
0
1
Transmit AIS Towards Remote End
Sends AIS on ports XL1, XL2, XOID towards the remote end. The
outgoing data stream which can be looped back through the local loop to
the system interface is not affected.
Description
Receive Transparent Mode, E1 only
For E1 mode this bit must be set to ´1´ for proper operation.
0
1
Disable AIS to Framer Interface
This bit must be set to ´1´for proper operation.
0
1
B
B
B
B
B
B
, PCM 30 or E1 mode.
, PCM 24 or T1/J1 mode .
, Reserved
,
, AIS is automatically inserted into the data stream to RDO if
OctalLIU
, Automatic AIS insertion is disabled. Furthermore, AIS insertion
can be initiated by programming bit MR2.SAIS.
Offset
xx1D
Offset
xx1E
TM
95
is in asynchronous state.
H
H
Register DescriptionMode Register 1
Rev. 1.0, 2005-06-02
PEF 22508 E
OctalLIU
Reset Value
Reset Value
00
00
TM
H
H