PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 74

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PEF 22508 E V1.1-G

Manufacturer Part Number
PEF 22508 E V1.1-G
Description
IC INTERFACE E1/T1/J1 LBGA-256
Manufacturer
Infineon Technologies
Series
OctalLIU™r
Datasheet

Specifications of PEF 22508 E V1.1-G

Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Current - Supply
370mA
Power (watts)
140mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-LSBGA
Includes
Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PEF22508EV1.1T
PEF22508EV11GXP
SP000029953
Figure 31
3.9.5
The received single rail bit stream from pin XDI or dual rail bit stream from the pins XDIP and XDIN are optionally
stored in the transmit elastic buffer, see
buffer. The functions are also equal to the receive side. Programming of the dual transmit buffer size is done by
DIC1.XBS(1:0) in the same way as programming of the dual receive buffer size by DIC1.RBS(1:0), see
The functions of the transmit buffer are:
Writing of received data from XDIP/XDIN is controlled by the internal transmit clock. Selection of FCLKX or FCLKR
is possible, see multiplexer “E” in
FCLKR.)
Reading of stored data is controlled by the clock generated either by the DCO-X circuitry or the externally
generated TCLK. With the de-jittered clock data is read from the dual transmit elastic buffer and are forwarded to
the transmitter. Reporting and controlling of slips is done according to the receive direction. Positive/negative slips
are reported in interrupt status bits ISR4.XSP and ISR4.XSN. If the transmit buffer is bypassed data is directly
transferred to the transmitter.
3.9.6
The transmitter includes a programmable pulse shaper to generate transmit pulse masks according to:
The transmit pulse shape (U
Data Sheet
Receive Line
Interface
Transmit Line
Interface
Clock adoption between framer transmit clock (FCLKX) and internally generated transmit route clock, see
Chapter
Compensation of input wander and jitter.
Reporting and controlling of slips
For T1: FCC68; ANSI T1. 403 1999, figure 4; ITU-T G703 11/2001, figure 10 (for different cable lengths), see
Figure 56
For E1: ITU-T G703 11/2001, figure 15 (for 0 m cable length) see
(for DCIM mode), see
XL1/XOID1
RL1/ROID
MCLK
XCLK
XL3
XL2
XL4
RL2
3.9.4.
Clocking and Data in Remote Loop Configuration
Dual Transmit Elastic Buffer
Programmable Pulse Shaper and Line Build-Out
and
Equalizer
Figure 33
Clocking Unit
Master
Figure 32
PULSE
for measurement configuration were R
DAC
Figure
) is programmed either
for measurement configuration were R
Shaper,
Pulse
LBO
Figure
29. (If the DCO-R output is selected, the DCO_R output is also output at
Recovery
Clock &
Data
DPLL
29. The tansmit elastic buffer is organized as the receive elastic
Buffer
JATT
74
Decoder
Encoder
H
load
Figure
= 100
DCO-X
load
55; ITU-T G703 11/2001, figure 20
Automatic Transmit
Clock Switching
= 120
recovered
receive clock
G
O c talLIU _rem ote_loop_c loc k ing
or R
Functional Description
F
Rev. 1.0, 2005-06-02
load
E
%
= 75
from
DCO-R
PEF 22508 E
OctalLIU
FCLKX
XDATA
FCLKR
TCLK
RDATA
Table
21:
TM

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