PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 34

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Table 1
Pin No. Ball
Data Sheet
No.
E3
E2
E3
E2
E3
E2
E3
E2
E3
E2
F5
F6
L7
M2
I/O Signals (cont’d)
Name
XPA1
XPB1
XPA1
XPB1
XPA1
XPB1
XPA1
XPB1
XPA1
XPB1
XPA2
XPB2
XPA3
XPB3
Pin Type Buffer
I
I
O
O
O
O
I
I
I
I
I/O
I/O
Type
PU
PU
–
–
–
–
PU
PU
PU
PU
PU/–
PU/–
34
Function
General Purpose Input (GPI), port 1
PC(1:2).XPC(3:0) = ´1001
The pin is set to input. The state of this input is reflected
in the register bits MFPI.XPA, MFPI.XPB or MFPI.XPC
respectively.
General Purpose Output High (GPOH), port 1
PC(1:2).XPC(3:0) = ´1010
The pin level is set fix to high level.
General Purpose Output Low (GPOL), port 1
PC(1:2).XPC(3:0) = ´1011
The pin level is set fix to high level.
Transmit Data Input Negative (XDIN), port 1
PC(1:2).XPC(3:0) = ´1101
Transmit data input negative for dual rail mode on
framer side (LIM3.DRX = ´1´). Depending on bit
DIC3.RESX latching of data is done with the rising or
falling edge of FCLKX.
Transmit Line Tristate, low active, port 1
XLT : PC(1:2).XPC(3:0) = ´1110
A low level on this port sets the transmit lines XL1/2 or
XDOP/N into tristate mode. This pin function is logically
OR´d with register bit XPM2.XLT.
Transmit Multifunction Pins A and B, port 2
Depending on programming of bits PC(1:2).XPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the OctalLIU
reset the ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESX
latching/transmission of data is done with the rising or
falling edge of FCLKX. If not connected, an internal pull-
up transistor ensures a high input level.
Each input function (TCLK, XDIN, XLT or XLT) may only
be selected once.
Selectable pin functions as described for port 1.
Transmit Multifunction Pins A and B, port 3
Depending on programming of bits PC(1:2).XPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the OctalLIU
reset the ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESX
latching/transmission of data is done with the rising or
falling edge of FCLKX. If not connected, an internal pull-
up transistor ensures a high input level.
Each input function (TCLK, XDIN, XLT or XLT) may only
be selected once.
Selectable pin functions as described for port 1.
b
b
b
b
.
´.
´.
.
b
´.
Rev. 1.0, 2005-06-02
Pin Descriptions
PEF 22508 E
OctalLIU
TM
TM
. After
. After
TM