PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 123

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Table 42
Name and Description
TCLK: Transmit Clock (Input)
A 2.048/8.192 MHz clock has to be sourced by the system if the internal generated transmit
clock (DCO-X) is not used. Optionally this input is used as a synchronization clock for the
DCO-X circuitry with a frequency of 2.048 MHz.
reserved
reserved
reserved
XCLK: Transmit Line Clock (Output)
Frequency: 2.048 MHz
XLT: Transmit Line Tristate control input, high active
With a high level on this port the transmit lines XL1/2 or XDOP/N are set directly into tristate.
This pin function is logically OR´d with register XPM2.XLT. See
GPI: General Purpose Input, low level
Value of this input is stored in register MFPI.
GPOH: General Purpose Output, high level
Pin is set fixed to high level
GPOL: General Purpose Output, low level
Pin is set fixed to low level
reserved
XDIN: Transmit Data In Negative
Negative transmit data in for dual rail mode
XLT: Transmit Line Tristate control input, low active
see XLT
reserved
Registers PC2 to PC3 have the same layout and description, but the 4 LSBs of PC3 are not used because only 2
MFPs in transmit direction exists.
The bits (3:0) of the register PC3 can be written and read, but are not valid.
Only one of the ports RPA, RPB or RPC must be configured as RTDMT.
Only one of the ports XPA or XPB must be configured as XLT or XLT.
The registers PC1, PC2 and PC4 have the reset values ´00
The Offset Addresses are listed in
Table 43
Register Short Name
PC2
PC3
Table 44
PC1
PC2
PC3
Data Sheet
XPC1 Constant Values (cont’d)
PCn Overview
Port Configuration Registers
7
RPC13
RPC23
RPC33
6
RPC12
RPC22
RPC32
Register Long Name
Port Configuration Register 2
Port Configuration Register 3
PCn
5
RPC11
RPC21
RPC31
Overview, for bit names refer to
4
RPC10
RPC20
RPC30
123
H
´, PC3 has the reset value ´F0
3
XPC13
XPC23
XPC33
Chapter
Port Configuration
3.9.1.
2
XPC12
XPC22
XPC32
Offset Address
xx81
xx82
H
H
1
XPC11
XPC21
XPC31
Register Description
H
Rev. 1.0, 2005-06-02
´.
Value
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Registers.
PEF 22508 E
Page Number
B
B
B
B
B
B
B
B
B
B
B
B
B
OctalLIU
0
XPC10
XPC20
XPC30
TM