PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 52

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Figure 15
After switching on the device (power-on), a reset signal has to be applied to TRS, which forces the TAP controller
into test logic reset state.
For normal operation without boundary scan access, the boundary reset pin TRS can be tied to the device reset
pin RES.
The boundary length is 247.
If no boundary scan operation is used, TRS has to be connected to RST or V
to be connected since pull-up transistors ensure high input levels in this case.
Test handling (boundary scan operation) is performed using the pins TCK (Test Clock), TMS (Test Mode Select),
TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, that means
TRS is connected to V
clock signal connected to TCK. "1" or "0" on TMS causes a transition from one controller state to another; constant
"1" on TMS leads to normal operation of the chip.
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out and enable) and
an I/O-pin (I/O) uses three cells (data in, data out and enable). Note that most functional output and input pins of
the OctalLIU
The desired test mode is selected by serially loading a 8-bit instruction code into the instruction register through
TDI (LSB first), see
EXTEST
Extest is used to examine the interconnection of the devices on the board. In this test mode at first all input pins
capture the current level on the corresponding external interconnection line, whereas all output pins are held at
constant values ("0" or "1"). Then the contents of the boundary scan is shifted to TDO. At the same time the next
scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan
contents and all input pins again capture the current external level afterwards, and so on.
Data Sheet
TM
Block Diagram of Test Access Port and Boundary Scan
are tested as I/O pins in boundary scan, hence using three cells.
Table
DD
TMS
TDO
TRS
TCK
TDI
or it remains unconnected due to its internal pull up. Test data at TDI is loaded with a
10. The test modes are:
TAP controller reset
clock
test
control
data in
enable
data
out
Generation
test signal generator
finite state machine
Clock
instruction register
TAP Controller
52
Reset
ID data out
control
bus
BD data out
BD data in
SS
. TMS, TCK and TDI do not need
F0115
Functional Description
Rev. 1.0, 2005-06-02
1
2
n
PEF 22508 E
OctalLIU
TM