PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 44

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Intel
Motorola
Data lines
n: even address
3.5.2
Two serial interfaces are included to enable device programming and controlling:- Slave Serial Control Interface
(SCI) - Slave Serial Peripheral Interface (SPI)
By using the SCI Interface, the OctalLIU
SHDSL- and ADSL-PHYs so that implementation of different line transmission technologies on the same line card
easily is possible. The SCI interface is a three-wire bus and optionally replaces the parallel processor interface to
reduce wiring overhead on the PCB, especially if multiple devices are used on a single board. Data on the bus is
HDLC encapsulated and uses a message-based communication protocol.
If SCI interface with multipoint to multipoint configuration is used, address pins A(5:0) are used for SCI source
(slave) address pin strapping, see
Note that after a reset writing into or reading from OctalLIU
possible until the PLL is locked: If the SCI-Interface is used no acknowledge message will be sent by the
OctalLIU
trace if the SPI interface is accessible, the micro controller should poll for example the register DSTR so long as
it read no longer the value ´F
3.5.2.1
The Serial Control Interface (SCI) is selected if IM(1:0) is strapped to ´11
The OctalLIU
Figure 49
parameters.
Figure 6
connections are realized between every OctalLIU
interfaces (SCI_TXD) of the OctalLIU
in
Figure 7
controller (half duplex). Here the data out pin of the SCI interfaces (SCI_TXD) of all OctalLIU
configured as an open Drain (oD), see configuration register bit PP in
(SCI_RXD, SCI_TXD) of each OctalLIU
common pull up resistor for the data line, all open Drain data out pins are building a wired And.
The Infineon proprietary Daisy-Chain approach is not supported
The group address of the SCI interface is ´00
to the group addresses of all other Infineon devices.
In case of multipoint to multipoint applications the 6 MSBs of the SCI source address will be defined by
pinstrapping of the address pins A5 to A0. The two LSBs of the SCI source address are constant ´10B´, see
Table
applications with point to point connections for the SCI interface the source address is not valid.
Because 14 bits are used for the register addresses in the SCI interface macro the two MSBs of the 16 bit wide
register addresses are set fixed to zero.
Data Sheet
Table
8. The SCI source address can be overwritten by a write command into the SCI configuration register. For
TM
8.
shows a first application using the SCI interfaces of some OctalLIU
shows an application with Multipoint to multipoint connections between the OctalLIU
shows the timing diagram of the SCI interface,
. If the SPI-Interface is used pin SDO has high impedance (SDO is pulled up by external resistor). To
Serial Micro Controller Interfaces
SCI Interface
TM
SCI interface is always a slave.
(Address n + 1)
(Address n)
D15
H
´.
Table
TM
s must be configured as push-pull (PP), see configuration register bit PP
TM
TM
2.
can be easily connected to Infineon interworking devices plus Infineon
are connected together to form a common data line. Together with a
H
´ after reset. Recommendation for configuring is ´C4
TM
D8
and the micro controller. Here the data out pins of the SCI
44
Table 56
TM
registers using the SCI- or SPI-Interface is not
(Address n)
(Address n + 1)
D7
gives the appropriate values of the timing
Table
H
´.
TM
8. The data out and data in pins
s where point to point full duplex
Functional Description
Rev. 1.0, 2005-06-02
TM
PEF 22508 E
H
s and the micro
´ to be different
D0
OctalLIU
TM
s must be
TM