PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 54

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Figure 16
3.5.5.1
If the (asynchronous) micro controller interface mode is selected by IM(1:0) the PLL must be configured
•
•
The SPI and SCI are synchronous interfaces and therefore need defined clocks immediately after reset, before
any configuration is done. So to enable access to serial interfaces, the clock MCLK must be active and must have
a defined frequency before reset becomes inactive. Dependent on the MCLK frequency the internal PLL must be
configured if the SCI- or SPI-Interface mode is selected by IM(1:0)
•
•
The configuration of the PLL by pinstrapping (see
way as by using the registers GCM5 and GCM6 if asynchronous micro controller interface mode (Intel or Motorola)
is selected. So calculation of the pinstrapping values can be done also by using the formulas in
the “flexible Master Clock Calculator” which is part of the software support of the OctalLIU
the serial interfaces are selected, pinstrapping of D(15:5) configure the PLL directly, so changes causes always a
reset of the PLL.
The conditions to trigger a reset of the central clock PLL are listed in
reset of the clock system.
Data Sheet
By programming of the registers GCM5 and GCM6 in “flexible master clocking mode”. Every change of the
contents of these registers - the divider factors N and M of the PLL - causes a reset of the PLL. Switching
between E1 and T1 modes in arbitrary channels causes a reset of the clock unit but not of the PLL itself.
Or by enabling of the ”fixed mode”: GCM2.VFREQ_EN = ´0´ (GCM2). Programming of registers GCM5 and
GCM6 is not necessary. Any programming of GCM5 and GCM6 does NOT cause a reset of the PLL. Switching
between E1 and T1 modes (for all channels) causes a reset of the clock unit but not of the PLL itself.
By strapping of the pins D(15:5) if “fixed mode” is not enabled (GCM2.VFREQ_EN = ´1´), see also
Because “fixed mode” is not enabled after reset, pinstrapping at D(15:5) is always necessary! Every new value
at this pins causes a reset of the PLL. Configuring by the registers GCM5 and GCM6 is not taken into account
and causes not a reset of the PLL
Or by enabling of the ” fixed mode”.This is only allowed if the values of N and M defined by pinstrapping are
identical to that values which are internally used for the “fixed mode”. That avoids changing of N and M by
switching into the ”fixed mode” and therefore a new reset of the PLL. (A new reset of the PLL can cause a hang
up of the whole system!) In ”fixed mode” the values are: N = ´33
D(10:5) = ´HLLLLH´, D(15:11) = ´LLLLL´. In ”fixed mode” programming of registers GCM1 to GCM8 is no
longer necessary and values at the pins D(15:5) are no longer taken into account and causes NOT a reset of
the PLL. A switching between E1 and T1 modes causes a reset of the clock unit but not of the PLL itself.
MCLK
Flexible Master Clock Unit
PLL (Reset and Configuring)
D(15:5)
PLL
IM(1:0)
Flexible Master Clock Unit
GCM1...GCM8
Table
54
2) in case of serial interface modes is done in the same
10
´, M = ´0
Table
11. Every reset of the PLL causes a
10
E1 Clocks
´ so that the pinstrapping must be:
T1 / J1
Clocks
Functional Description
TM
O c talFA LC __F0116
Rev. 1.0, 2005-06-02
channel
, see
1 to 8
GCM6
PEF 22508 E
Chapter
OctalLIU
or by using
Table
8.3. If
TM
2.