PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 153

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Field
LLBSC
RSN
RSP
Interrupt Status Register 4
All bits are reset when ISR4 is read. If bit GCR.VIS is set, interrupt statuses in ISR4 are flagged although they are
masked by register IMR4. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS, see
ISR4
Interrupt Status Register 4
Field
XSP
Data Sheet
Bits
3
1
0
Bits
7
Chapter
Type
rsc
rsc
rcs
Type
rsc
3.5.3.
Description
Line Loop-Back Status Change, T1/J1 only
In E1 mode this bit is not valid and ISR1.LLBSC is used instead.
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
•
•
Receive Slip Negative
The frequency of the receive route clock is greater than the frequency of
the receive system interface working clock based on 2.048 MHz. A frame
is skipped. It is set during alarm simulation. See
Receive Slip Positive
The frequency of the receive route clock is less than the frequency of the
receive system interface working clock based on 2.048 MHz. A frame is
repeated. It is set during alarm simulation. See
Description
Transmit Slip Positive
The frequency of the transmit clock is less than the frequency of the
transmit system interface working clock based on 2.048 MHz. A frame is
repeated. After a slip has performed writing of register XC1 is not
necessary.
LCR1.EPRM = 0: This bit is set, if the LLB activate signal or the LLB
deactivate signal, respectively, is detected over a period of 25 ms with
a bit error rate less than 10
detection status is left, i.e., if the bit error rate exceeds 10
detection status can be read from the LSR2.LLBAD / LSR2.LLBDD in
E1 or LSR1.LLBAD / LSR1.LLBDD in T1/J1 mode, respectively.
PRBS Status Change LCR1.EPRM = ´1´: With any change of state of
the PRBS synchronizer this bit is set. The current status of the PRBS
synchronizer is indicated in LSR2.LLBAD (E1) or LSR1.LLBAD
(T1/J1).
Offset
xx6C
153
H
Register DescriptionInterrupt Status Register 4
-2
. The LLBSC bit is also set, if the current
Chapter
Chapter
Rev. 1.0, 2005-06-02
3.7.10.
PEF 22508 E
3.7.10.
-2
OctalLIU
Reset Value
. The actual
00
TM
H