PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 26

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Table 1
Pin No. Ball
Data Sheet
No.
N11
N10
P11
P10
N14
N13
P14
P13
I/O Signals (cont’d)
Name
XL1.5
XOID5
XL2.5
XL3.5
XL4.5
XL1.6
XOID6
XL2.6
XL3.6
XL4.6
Pin Type Buffer
O
(analog)
O
O
(analog)
I (analog) –
I (analog) –
O
(analog)
O
O
(analog)
I (analog) –
I (analog) –
Type
–
–
–
–
–
–
26
Function
Transmit Line 1, port 5
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Transmit Optical Interface Data, port 5
cycle on both transitions of XCLK5 according to the CMI
coding. Output polarity is selected by bit LIM0.XDOS
(after reset: data is sent active high). The single-rail
mode is selected if LIM1.DRS is set and MR0.XC1 is
cleared. After reset this pin is in high-impedance state
until register LIM1.DRS is set and XPM2.XLT is cleared.
Transmit Line 2, port 5
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Transmit Line 3, port 5
Analog transmit input 1.
Transmit Line 4, port 5
Analog transmit input 2.
Transmit Line 1, port 6
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Transmit Optical Interface Data, port 6
. Data in CMI code is shifted out with 50% or 100% duty
cycle on both transitions of XCLK6 according to the CMI
coding. Output polarity is selected by bit LIM0.XDOS
(after reset: data is sent active high). The single-rail
mode is selected if LIM1.DRS is set and MR0.XC1 is
cleared. After reset this pin is in high-impedance state
until register LIM1.DRS is set and XPM2.XLT is cleared.
Transmit Line 2, port 6
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Transmit Line 3, port 6
Analog transmit input 1.
Transmit Line 4, port 6
Analog transmit input 2.
Data in CMI code is shifted out with 50% or 100% duty
Rev. 1.0, 2005-06-02
Pin Descriptions
PEF 22508 E
OctalLIU
TM