PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 182

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

7.3
After reset, the OctalLIU
Table 68
Register
LIM0, LIM1,
PCD, PCR
XPM(2:0)
IMR(7:0)
GCR
CMR1
CMR2
PC(3:1)
PC5
GCM(6:1)
GPC(5:3)
GPC6
CMR(6:4)
GPC2
TXP(16:1)
INBLDTR
ALS
PRBSTS(4:1)
7.4
E1 Configuration
For a correct start up of the primary access interface a set of parameters specific to the system and hardware
environment must be programmed after reset goes inactive. Both the basic and the operational parameters must
be programmed before the activation procedure of the PCM line starts. Such procedures are specified in ITU-T
and ETSI recommendations (e.g. fault conditions and consequent actions). Setting optional parameters primarily
makes sense when basic operation via the PCM line is guaranteed.
important parameters in terms of signals and control bits which are to be programmed in one of the above steps.
The sequence is recommended but not mandatory. Accordingly, parameters for the basic and operational set up,
for example, can be programmed simultaneously. The bit MR1.PMOD should always be kept low (otherwise T1/J1
mode is selected).
Data Sheet
Device Initialization
Initial Values after Reset
Device Configuration in E1 Mode
Reset Value
´00
´00
´40
´FF
´00
´00
´00
´00
´00
´00
GCM2 = ´10
others ´00
´65
´07
´00
´00
TXP(1:8) = ´38
TXP(9:16) = ´00
´00
´00
all ´00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
´, ´00
´, ´00
´, ´03
´
´
´
´, ´F0
´, ´00
´
´, ´43
´
´
´
´
´
´
H
TM
´
H
H
H
H
H
H
is initialized for E1 with register values listed in the following table.
H
´,
´
´, ´7B
´
´, ´21
´
´
H
´,
H
´
H
H
H
´ Source for RCLK1 up to RCLK7 are the appropriate channels (only valid for
´ E1 Transmit pulse template for 0 m but with unreduced amplitude (note that
´
Meaning
Slave Mode, local loop off
Analog interface selected; remote loop off; Pulse count for LOS detection
cleared; Pulse count for LOS recovery cleared
transmitter is in tristate mode)
All interrupts are disabled
Internal second timer, power on
RCLK output: DPLL clock, DCO-X enabled, DCO-X internal reference clock
RCLK selected, XCLK selected
Functions of ports RP(A to B) are reserved, function of port RPC is RCLK
output (but is only pulled up, because PC5.CRP = ´0´ after reset), functions
of ports XP(A to B) are reserved.
FCLKR, FCLKX, RCLK configured to inputs,
“Flexible master clocking mode” selected
COMP = ´0´)
QuadLIU compatible system interface multiplexed modes are selected,
source for RCLK8 is channel 8 (both only valid for COMP = ´0´)
Recovered line clock drives RCLK
Source for SEC and RCLK1 is channel 1
This registers are not used after reset because XPM2.XPDIS = ´0´
Minimum In-band loop detection time
No automatic loop switching is performed
No time slots are selected for PRBS pattern
182
Table 69
gives an overview of the most
Operational Description
Rev. 1.0, 2005-06-02
PEF 22508 E
OctalLIU
TM