PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 91

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

Field
SSYF
IC
Interrupt Mask Register 1
Each interrupt source can generate an interrupt signal on port INT (characteristics of the output stage are defined
by register IPC). A “1” in a bit position of IMR(1:4), IMR(6:7) sets the mask active for the interrupt status in ISR(1:4),
ISR(6:7). Masked interrupt statuses neither generate a signal on INT, nor are they visible in register GIS.
Moreover, they are- not displayed in the interrupt status register if bit GCR.VIS is cleared- displayed in the interrupt
status register if bit GCR.VIS is set, see
IMR1
Interrupt Mask Register 1
Field
LLBSC
XLSC
Data Sheet
Bits
2
1:0
Bits
7
1
Type
rw
rw
Type
rw
rw
Description
Select SYNC Frequency
Only applicable in master mode (LIM0.MAS = ´1´) and bit CMR2.DCF is
cleared, see also Table 9.
0
1
Interrupt Port Configuration
These bits define the function of the interrupt output pin INT.
X0
01
11
Description
Interrupt Mask Bit LLBSC
Each interrupt source can generate an interrupt signal on port INT.
Characteristics of the output stage are defined by register IPC. A ´1´ in a
bit position of IMR(7:0) sets the mask active for the interrupt status in the
registers ISR. Mask interrupt statuses neither generate a signal on INT,
not are they visible in register GIS. Moreover they are not displayed in the
interrupt status register if bit GCR.VIS is cleared; they are displayed in the
interrupt status register if bit GCR.VIS is set.
The bit IMR1.LLBSC is only valid in E1 mode. For T1/J1 mode the
equivalent bit is in IMR3.LLBSC.
Interrupt Mask Bit XLSC
Chapter
B
B
B
B
B
, Reference clock on port SYNC is 2.048 MHz
, Reference clock on port SYNC is 8 kHz
, Open drain output
, Push/pull output, active low
, Push/pull output, active high
3.5.3.
Offset
xx15
91
H
Register DescriptionInterrupt Mask Register 1
Rev. 1.0, 2005-06-02
PEF 22508 E
OctalLIU
Reset Value
FF
TM
H