PEF 22508 E V1.1-G Infineon Technologies, PEF 22508 E V1.1-G Datasheet - Page 63

• Manufacturer Part Number: PEF 22508 E V1.1-G
• Description: IC INTERFACE E1/T1/J1 LBGA-256
• Manufacturer: Infineon Technologies
• Series: OctalLIU™r

Specifications of PEF 22508 E V1.1-G

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Current - Supply: 370mA
• Power (watts): 140mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LSBGA
• Includes: Automatic Protection Switching, Clock Generation, Power-Down, Transmit Line Monitor, Tristate Function
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF22508EV1.1T; PEF22508EV11GXP; SP000029953

either on the extracted receive clock RCLK or on a 2.048 MHz/8 kHz or 1.544 MHz/8 kHz clock provided on pin
SYNC (8 kHz in master mode only). The jitter attenuated DCO-R output clock can be output on pin RCLK and
FCLKR. Optionally an 8 kHz clock is provided on pin SEC FSC.
For jitter attenuation the received data is written into the receive elastic buffer with the recovered clock sourced by
the clock & data recovery and are read out with the de-jittered clock sourced by DCO-R.
If the receive elastic buffer is read out directly with the recovered receive clock, no jitter attenuation is performed.
If the receive elastic buffer is read out with the receive framer clock FCLKR, the receive elastic buffer performs a
clock adoption from the recovered receive clock to FCLKR.
The DCO-R circuitry attenuates the incoming jittered clock starting at its corner frequency with 20 dB per decade
fall-off. Wander with a jitter frequency below the corner frequency is passed unattenuated. The intrinsic jitter in the
absence of any input jitter is < 0.02 UI.
The corner frequency of the DCO-R can be configured in a wide range, see
attenuator PLL in the transmit path, so called as DCO-X, is equivalent to the DCO-R so that the principle for its
configuring is the same.
Table 18
CMR6.DCOCOMPN CMR2.ECFAR
X
X
0
1
After reset the corner frequencies are 2 Hz in E1 and 6 Hz in T1/J1 mode and can be switched to 0.2 Hz in E1
mode or 0.6 Hz n T1 mode by setting the register bit LIM2.SCF for the DCO-R or the register bit CMR5.SCFX for
the DCO-X respectively. A logical table builds the integral (I) and proportional (P) parameter for the PI filter of the
DCO-R or DCO-X, see
If the register bits CMR2.ECFAR or CMR2.ECFAX are set for the DCO-R or the DCO-X respectively, the corner
frequencies can be configured in a range between 2 Hz and 0.2 Hz using the register bits CMR3.CFAR(3:0) or
CMR3.CFAX(3:0) respectively, see CMR3,
parameter for the PI filter of the DCO-R or DCO-X out of the settings in CMR3.CFAR(3:0) or CMR3.CFAX(3:0)
respectively.
If additionally to CMR2.ECFAR or CMR2.ECFAX the bit CMR6.DCOCOMPN (CMR6) is set, which is valid for the
DCO-R and the DCO-X, the corner frequencies and attenuation factors can be programmed in a wide range using
the register bits CMR3.CFAR(3:0) and CMR4.IAR(4:0) for the DCO-R and CMR3.CFAX(3:0) and CMR5.IAX(4:0)
for the DCO-X. The settings in CMR3.CFAR(3:0)/CFAX(3:0) build the proportional parameter, the settings in
CMR4.IAR(4:0) and CMR5.IAX(4:0) build the integral parameter for the PI filters, independent from another.
Data Sheet
Overview DCO-R (DCO-X) Programming
(CMR2.ECFAX)
0
0
1
1
Figure
23.
LIM2.SCF
(CMR6.SCFX)
0
1
X
X
CMR4
and CMR5. A logical table builds the integral and proportional
63
CMR3.CFAR(3:0)
(CMR3.CFAX(3:0))
Not used
Not used
7
´4
´0
as proportional
parameter
´9
´8
´6
´4
H
H
H
H
H
H
H
´
´
´ ...´F
´
´
´
´
H
´ , used
Table 18
CMR4.IAR(3:0)
(CMR5.IAX(4:0))
Not used
Not used
Not used
´00
used as integral
parameter
´19
´13
´12
´0F
H
H
H
H
H
´ ...´1F
´
´
´
´
and
Functional Description
H
´
Rev. 1.0, 2005-06-02
Figure
PEF 22508 E
Corner-
frequencies
of DCO-R
(DCO-X)
E1 / T1
2 Hz / 6 Hz
0.2 Hz / 0.6 Hz
0.2 Hz / 0.6 Hz
2 Hz / 6 Hz
Range 0.2 Hz
... 20 Hz
0.2 Hz
0.6 Hz
2 Hz
6Hz
OctalLIU
23. The jitter
TM