MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 100

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

IE — Interrupt Enable
WCM — Wait Clock Mode
BCR2 — BDLC Control Register 2
ALOOP — Analog Loopback Status
DLOOP — Digital Loopback Mode
100
MOTOROLA
RESET:
Determines whether the BDLC will generate CPU interrupt requests in the run mode. It does not affect
CPU interrupt requests when exiting the BDLC stop or BDLC wait modes.
Determines the operation of the BDLC during CPU wait mode
Controls transmitter operations of the BDLC.
Sets the BDLC state machine to a known state after the off-chip analog transceiver has been put in loop
back mode.
Determines the RxPD source and can isolate bus fault conditions. If a fault condition is detected on the
bus, RxPD can be disconnected from the analog transceiver’s receive output and connected to TxPD
to determine if the fault is in the digital block or elsewhere on the J1850 bus.
0 = Disable interrupt requests from BDLC
1 = Enable interrupt requests from BDLC
0 = Run BDLC internal clocks during CPU wait mode
1 = Stop BDLC internal clocks during CPU wait mode
0 = Off-chip analog transceiver has been taken out of analog loopback mode
1 = Off-chip analog transceiver has been put into analog loopback mode
0 = RxPD is connected to the analog transceiver’s receive output. The BDLC is taken out of digital
1 = RxPD is connected to TxPD. The BDLC is now in digital loopback mode of operation. The an-
loopback mode and can now drive and receive from the J1850 bus normally if ALOOP is not set.
alog transceiver’s transmit input is still driven by TxPD.
ALOOP
Bit 7
1
DLOOP
MCU Clock Frequency (
MCU Clock Frequency (
Table 33 BDLC Rate Selection for Integer Frequencies
Table 32 BDLC Rate Selection for Binary Frequencies
6
1
1.048576 MHz
2.09715 MHz
4.19430 MHz
8.38861 MHz
1.00000 MHz
2.00000 MHz
4.00000 MHz
8.00000 MHz
RX4XE
5
0
(f
(f
BDLC
BDLC
NBFS
f
f
TCLKS
TCLKS
4
0
= 1.048576 MHz)
= 1.000000 MHz)
)
)
TEOD
3
0
R1
R1
0
0
1
1
0
0
1
1
TSIFR
2
0
R0
R0
0
1
0
1
0
1
0
1
TMIFR1
Division
Division
1
0
1
2
4
8
1
2
4
8
MC68HC912B32TS/D
TMIFR0
Bit 0
MC68HC912B32
0
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