MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 114

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

RST — Module Reset Bit
TSTOUT — Multiplex Output of TST[3:0] (Factory Use)
TST[3:0] — Test Bits 3 to 0 (Reserved)
PORTAD — Port AD Data Input Register
PAD[7:0] — Port AD Data Input Bits
ADR0H — ATD Converter Result Register 0
ADR1H — ATD Converter Result Register 1
ADR2H — ATD Converter Result Register 2
ADR3H — ATD Converter Result Register 3
ADR4H — ATD Converter Result Register 4
ADR5H — ATD Converter Result Register 5
ADR6H — ATD Converter Result Register 6
ADR7H — ATD Converter Result Register 7
ADRxH[7:0] — ATD Conversion Result
15.3 ATD Mode Operation
114
MOTOROLA
RESET:
RESET:
$007x
When set, this bit causes all registers and activity in the module to assume the same state as out of
power-on reset (except for ADPU bit in ATDCTL2, which remains set, allowing the ATD module to re-
main enabled).
Selects one of 16 reserved factory testing modes.
After reset these bits reflect the state of the input pins.
May be used for general-purpose digital input. When the software reads PORTAD, it obtains the digital
levels that appear on the corresponding port AD pins. Pins with signals not meeting V
cations will have an indeterminate value. Writes to this register have no meaning at any time.
The reset condition for these registers is undefined.
These bits contain the left justified, unsigned result from the ATD conversion. The channel from which
this result was obtained is dependent on the conversion mode selected. These registers are always
read-only in normal mode.
STOP — causes all clocks to halt (if the S bit in the CCR is zero). The system is placed in a minimum-
power standby mode. This aborts any conversion sequence in progress. During STOP recovery, the
ATD must delay for the STOP recovery time (t
WAIT — ATD conversion continues unless AWAI bit in ATDCTL2 register is set.
BDM — Debug options available as set in register ATDCTL3.
USER — ATD continues running unless ADPU is cleared.
ADPU — ATD operations are stopped if ADPU = 0, but registers are accessible.
PAD7
Bit 7
Bit 7
Bit 7
–
–
PAD6
6
–
6
6
–
PAD5
5
–
5
5
–
PAD4
4
–
4
4
–
SR
) before initiating a new ATD conversion sequence.
PAD3
3
–
3
3
–
PAD2
2
–
2
2
–
PAD1
1
–
1
1
–
MC68HC912B32TS/D
PAD0
Bit 0
Bit 0
Bit 0
MC68HC912B32
–
–
IL
or V
IH
specifi-
$007A
$007C
$007E
$006F
$0070
$0072
$0074
$0076
$0078