MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 80

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

PEDGE — Pulse Accumulator Edge Control
CLK1, CLK0 — Clock Select Register
PAOVI — Pulse Accumulator Overflow Interrupt Enable
PAI — Pulse Accumulator Input Interrupt Enable
PAFLG — Pulse Accumulator Flag Register
PAOVF — Pulse Accumulator Overflow Flag
PAIF — Pulse Accumulator Input Edge Flag
80
MOTOROLA
RESET:
For PAMOD = 0 (event counter mode)
For PAMOD = 1 (gated time accumulation mode)
If the timer is not active (TEN = 0 in TSCR), there is no 64 clock since the E
by the timer prescaler.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as
an input clock to the timer counter. The change from one selected clock to the other happens immedi-
ately after these bits are written.
Read or write anytime.
When TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in
the PAFLG register.
Set when the 16-bit pulse accumulator overflows from $FFFF to $0000. This bit is cleared automatically
by a write to the PAFLG register with bit 1 set.
Set when the selected edge is detected at the pulse accumulator input pin. In event mode, the event
edge triggers PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the pulse
accumulator input pin triggers PAIF. This bit is cleared automatically by a write to the PAFLG register
with bit 0 set.
0 = Falling edges on the pulse accumulator input pin (PT7/PAI) cause the count to be incremented
1 = Rising edges on the pulse accumulator input pin cause the count to be incremented
0 = Pulse accumulator input pin high enables E 64 clock to pulse accumulator and the trailing fall-
1 = Pulse accumulator input pin low enables E 64 clock to pulse accumulator and the trailing rising
0 = Interrupt inhibited
1 = Interrupt requested if PAOVF is set
0 = Interrupt inhibited
1 = Interrupt requested if PAIF is set
ing edge on the pulse accumulator input pin sets the PAIF flag.
edge on the pulse accumulator input pin sets the PAIF flag.
Bit 7
0
0
CLK1
0
0
1
1
6
0
0
CLK0
0
1
0
1
5
0
0
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
Table 27 Clock Selection
4
0
0
Selected Clock
3
0
0
2
0
0
PAOVF
1
0
MC68HC912B32TS/D
64 clock is generated
PAIF
Bit 0
MC68HC912B32
0
$00A1