MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 79
MC68HC912B32MFU8
Manufacturer Part Number
MC68HC912B32MFU8
Description
16-Bit Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912B32MFU8.pdf
(128 pages)
- Current page: 79 of 128
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TC3 — Timer Input Capture/Output Compare Register 3
TC4 — Timer Input Capture/Output Compare Register 4
TC5 — Timer Input Capture/Output Compare Register 5
TC6 — Timer Input Capture/Output Compare Register 6
TC7 — Timer Input Capture/Output Compare Register 7
PACTL — Pulse Accumulator Control Register
PAEN — Pulse Accumulator System Enable
PAMOD — Pulse Accumulator Mode
MC68HC912B32
MC68HC912B32TS/D
RESET:
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value
of the free-running counter when a defined transition is sensed by the corresponding input capture edge
detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to these registers have no meaning
or effect during input capture. All timer input capture/output compare registers are reset to $0000.
Read or write anytime.
PAEN is independent from TEN.
0 = Pulse accumulator system disabled
1 = Pulse accumulator system enabled
0 = Event counter mode
1 = Gated time accumulation mode
Bit 15
Bit 15
Bit 15
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
PAEN
14
14
14
14
14
6
6
6
6
6
6
6
6
6
6
6
0
PAMOD
13
13
13
13
13
5
5
5
5
5
5
5
5
5
5
5
0
PEDGE
12
12
12
12
12
4
4
4
4
4
4
4
4
4
4
4
0
CLK1
11
11
11
11
11
3
3
3
3
3
3
3
3
3
3
3
0
CLK0
10
10
10
10
10
2
2
2
2
2
2
2
2
2
2
2
0
PAOVI
1
9
1
1
9
1
1
9
1
1
9
1
1
9
1
1
0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
PAI
0
$009A–$009B
$009C–$009D
$009E–$009F
$0096–$0097
$0098–$0099
MOTOROLA
$00A0
79
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