MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 104

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

BDR — BDLC Data Register
BARD — BDLC Analog Roundtrip Delay Register
ATE — Analog Transceiver Enable
RXPOL — Receive Pin Polarity
BO[3:0] — BARD Offset
104
MOTOROLA
RESET:
RESET:
Used to pass data to be transmitted to the J1850 bus from the CPU to the BDLC. It is also used to pass
data to the CPU. Each data byte (after the first one) should be written only after a “Tx Data Register
Empty” (TDRE) interrupt has occurred, or the BSVR register has been polled indicating this condition.
Data read from this register will be the last data byte received from the J1850 bus and should be read
only after a “Rx Data Register Full” (RDRF) or a “Received IFR Byte” (RXIFR) interrupt has occurred,
or the BSVR register has been polled indicating this condition.
To stop a transmission that is already in progress simply stop loading more data into the BDR. This will
cause a transmitter underrun error and the BDLC will automatically disable the transmitter on the next
non-byte boundary.
Programs the BDLC to compensate for various delays of external transceivers. Read anytime. May be
written once in normal modes or written anytime in special mode.
This bit selects the polarity of the incoming signal on the receive pin.
These bits are used to compensate for the analog transceiver roundtrip delay. The following table
shows the expected transceiver delay with respect to BARD offset values:
0 = Select off-chip analog transceiver
1 = Select on-board analog transceiver
0 = Select inverted polarity, where external transceiver inverts the receive signal.
1 = Select normal/true polarity; true non-inverted signal from J1850 bus, i.e., the external transceiv-
er does not invert the receive signal.
Bit 7
Bit 7
ATE
D7
–
1
This device does not contain an on-board transceiver. The ATE bit should be pro-
grammed to a logic zero for proper operation.
RXPOL
D6
6
–
6
1
Table 36 Offset Bit Values and Transceiver Delay
(BO3, BO2, BO1, BO0)
BARD Offset Bits
D5
5
–
5
0
0
0000
0001
0010
0011
0100
D4
4
–
4
0
0
NOTE
Expected Delay ( s)
BO3
D3
3
–
3
0
10
11
12
13
9
BO2
D2
2
–
2
1
BO1
D1
1
–
1
1
MC68HC912B32TS/D
Bit 0
Bit 0
BO0
D0
MC68HC912B32
–
1
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