MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 82
MC68HC912B32MFU8
Manufacturer Part Number
MC68HC912B32MFU8
Description
16-Bit Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912B32MFU8.pdf
(128 pages)
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DDRT — Data Direction Register for Timer Port
12.2 Timer Operation in Modes
82
MOTOROLA
RESET:
Read or write anytime.
The timer forces the I/O state to be an output for each timer port pin associated with an enabled output
compare. In these cases the data direction bits will not be changed but have no affect on the direction
of these pins. The DDRT will revert to controlling the I/O direction of a pin when the associated timer
output compare is disabled. Input captures do not override the DDRT settings.
STOP:
BDM:
WAIT:
NORMAL: Timer keeps running, unless TEN = 0
TEN = 0:
PAEN = 0: All pulse accumulator operations are stopped, registers may be accessed.
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
DDT7
Bit 7
0
Timer is off since both PCLK and ECLK are stopped.
Timer keeps running, unless TSBCK = 1
Counters keep running, unless TSWAI = 1
All timer operations are stopped, registers may be accessed.
Gated pulse accumulator 64 clock is also disabled.
DDT6
6
0
DDT5
5
0
DDT4
4
0
DDT3
3
0
DDT2
2
0
DDT1
1
0
MC68HC912B32TS/D
DDT0
Bit 0
MC68HC912B32
0
$00AF
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