MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 110
MC68HC912B32MFU8
Manufacturer Part Number
MC68HC912B32MFU8
Description
16-Bit Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912B32MFU8.pdf
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ATDCTL4 — ATD Control Register 4
SMP1, SMP0 — Select Sample Time
PRS4, PRS3, PRS2, PRS1, PRS0 — Select Divide-By Factor for ATD P-Clock Prescaler.
110
MOTOROLA
RESET:
The ATD control register 4 is used to select the clock source and set up the prescaler. Writes to the ATD
control registers initiate a new conversion sequence. If a write occurs while a conversion is in progress,
the conversion is aborted and ATD activity halts until a write to ATDCTL5 occurs.
These bits are used to select one of four sample times after the buffered sample and transfer has oc-
curred. Total conversion time depends on initial sample time (two ATD clocks), transfer time (two ATD
clocks), final sample time (programmable, refer to Table 39), and resolution time (ten ATD clocks).
The binary value written to these bits (1 to 31) selects the divide-by factor for the modulo counter-based
prescaler. The P clock is divided by this value plus one and then fed into a 2 circuit to generate the
ATD module clock. The divide-by-two circuit insures symmetry of the output clock signal. Clearing these
bits causes the prescale value to default to one which results in a 2 prescale factor. This signal is then
fed into the 2 logic. The reset state divides the P clock by a total of four and is appropriate for nominal
operation between 2 MHz and 8 MHz bus rate. Table 40 shows the divide-by operation and the appro-
priate range of system clock frequencies.
SMP1
Bit 7
0
0
1
1
0
0
FRZ1 FRZ0
SMP0
0
0
1
1
SMP1
Table 38 ATD Response to Background Debug Enable
0
1
0
1
6
0
0
1
0
1
Table 39 Final Sample Time Selection
SMP0
5
0
16 ATD clock periods
2 ATD clock periods
4 ATD clock periods
Final Sample Time
8 ATD clock periods
Continue conversions in active background mode
Finish current conversion, then freeze
PRS4
4
0
Freeze when BDM is active
ATD Response
Reserved
PRS3
3
0
Total 8-Bit Conversion Time
PRS2
2
0
16 ATD clock periods
18 ATD clock periods
22 ATD clock periods
30 ATD clock periods
PRS1
1
0
MC68HC912B32TS/D
PRS0
Bit 0
MC68HC912B32
1
$0064
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